Issued Patents All Time
Showing 51–75 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6218688 | Schottky diode with reduced size | Alexander Kalnitsky, Pavel Poplevine | 2001-04-17 |
| 6215698 | Flash eprom with byte-wide erasure | Hosam Haggag | 2001-04-10 |
| 6208557 | EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming | Alexander Kalnitsky | 2001-03-27 |
| 6197671 | Multiple finger polysilicon gate structure and method of making | — | 2001-03-06 |
| 6190968 | Method for forming EPROM and flash memory cells with source-side injection | Alexander Kalnitsky, Christoph Pichler | 2001-02-20 |
| 6184557 | I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection | Pavel Poplevine, Alexander Kalnitsky, Hengyang (James) Lin | 2001-02-06 |
| 6184552 | Non-volatile memory cell with non-trenched substrate | Alexander Kalnitsky | 2001-02-06 |
| 6184099 | Low cost deep sub-micron CMOS process | Christopher I. Michael | 2001-02-06 |
| 6180994 | Array of sidewall-contacted antifuses having diffused bit lines | Alexander Kalnitsky | 2001-01-30 |
| 6177315 | Method of fabricating a high density EEPROM array | Alexander Kalnitsky | 2001-01-23 |
| 6169310 | Electrostatic discharge protection device | Alexander Kalnitsky, Pavel Poplevine, Hengyang (James) Lin | 2001-01-02 |
| 6166421 | Polysilicon fuse that provides an open current path when programmed without exposing the fuse to the environment | Alexander Kalnitsky | 2000-12-26 |
| 6157574 | Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data | Alexander Kalnitsky | 2000-12-05 |
| 6146962 | Method for forming a DRAM cell with a stacked capacitor | Alexander Kalnitsky | 2000-11-14 |
| 6136635 | Method for forming a bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region | Min-hwa Chi | 2000-10-24 |
| 6137723 | Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure | Alexander Kalnitsky | 2000-10-24 |
| 6137724 | Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages | Alexander Kalnitsky | 2000-10-24 |
| 6137722 | Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors | Alexander Kalnitsky | 2000-10-24 |
| 6137721 | Memory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasure | Alexander Kalnitsky | 2000-10-24 |
| 6130840 | Memory cell having an erasable Frohmann-Bentchkowsky memory transistor | Alexander Kalnitsky | 2000-10-10 |
| 6122204 | Sense amplifier having a bias circuit with a reduced size | Pavel Poplevine, Alexander Kalnitsky | 2000-09-19 |
| 6118157 | High voltage split gate CMOS transistors built in standard 2-poly core CMOS | — | 2000-09-12 |
| 6110797 | Process for fabricating trench isolation structure for integrated circuits | Jeff Perry | 2000-08-29 |
| 6087211 | Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors | Alexander Kalnitsky | 2000-07-11 |
| 6083791 | Self-aligned stacked gate etch process for fabricating a two-transistor EEPROM cell | — | 2000-07-04 |