Issued Patents All Time
Showing 26–50 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6563731 | EEPROM memory cell array embedded on core CMOS | — | 2003-05-13 |
| 6525397 | Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology | Alexander Kalnitsky, Pavel Poplevine | 2003-02-25 |
| 6509606 | Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process | Richard B. Merrill, Min-hwa Chi | 2003-01-21 |
| 6507516 | EEPROM memory cell embedded on core CMOS for analog applications | — | 2003-01-14 |
| 6498084 | Method of forming high density EEPROM cell | — | 2002-12-24 |
| 6482723 | Method for forming self-aligned floating gates | — | 2002-11-19 |
| 6420217 | Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology | Alexander Kalnitsky, Pavel Poplevine | 2002-07-16 |
| 6414872 | Compact non-volatile memory device and memory array | Pascale Francis | 2002-07-02 |
| 6384398 | CMOS compatible pixel cell that utilizes a gated diode to reset the cell | Alexander Kalnitsky, Pavel Poplevine | 2002-05-07 |
| 6380571 | CMOS compatible pixel cell that utilizes a gated diode to reset the cell | Alexander Kalnitsky, Pavel Poplevine | 2002-04-30 |
| 6380054 | Schottky diode with reduced size | Alexander Kalnitsky, Pavel Poplevine | 2002-04-30 |
| 6368917 | Methods of fabricating floating gate semiconductor device with reduced erase voltage | Alexander Kalnitsky | 2002-04-09 |
| 6365463 | Method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up | Alexander Kalnitsky | 2002-04-02 |
| 6362050 | Method for forming a non-volatile memory cell that eliminates substrate trenching | Alexander Kalnitsky | 2002-03-26 |
| 6362023 | Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture | Alexander Kalnitsky | 2002-03-26 |
| 6327187 | EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming | Alexander Kalnitsky | 2001-12-04 |
| 6300220 | Process for fabricating isolation structure for IC featuring grown and buried field oxide | — | 2001-10-09 |
| 6277724 | Method for forming an array of sidewall-contacted antifuses having diffused bit lines | Alexander Kalnitsky | 2001-08-21 |
| 6271560 | Single-poly EPROM cell with CMOS compatible programming voltages | Alexander Kalnitsky | 2001-08-07 |
| 6262460 | Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor | Alexander Kalnitsky, Pavel Poplevine | 2001-07-17 |
| 6249010 | Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture | Alexander Kalnitsky | 2001-06-19 |
| 6238979 | Process for fabricating EEPROM memory cell array embedded on core CMOS | — | 2001-05-29 |
| 6236082 | Floating gate semiconductor device with reduced erase voltage | Alexander Kalnitsky | 2001-05-22 |
| 6229739 | Sense amplifier having a bias circuit with a reduced size | Pavel Poplevine, Alexander Kalnitsky | 2001-05-08 |
| 6225163 | Process for forming high quality gate silicon dioxide layers of multiple thicknesses | — | 2001-05-01 |