Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8871103 | Process of planarizing a wafer with a large step height and/or surface area features | Brett W. Busch, Anurag Jindal, Chia-Yen Ho, Thy Tran | 2014-10-28 |
| 8872252 | Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier | Anurag Jindal, Roger W. Lindsay, Eric Blomiley | 2014-10-28 |
| 8580690 | Process of planarizing a wafer with a large step height and/or surface area features | Brett W. Busch, Anurag Jindal, Chia-Yen Ho, Thy Tran | 2013-11-12 |