TT

Thy Tran

NT Nanya Technology: 2 patents #292 of 775Top 40%
Motorola: 1 patents #6,475 of 12,470Top 55%
Overall (All Time): #1,536,172 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8871103 Process of planarizing a wafer with a large step height and/or surface area features Brett W. Busch, Gowri Damarla, Anurag Jindal, Chia-Yen Ho 2014-10-28
8580690 Process of planarizing a wafer with a large step height and/or surface area features Brett W. Busch, Gowri Damarla, Anurag Jindal, Chia-Yen Ho 2013-11-12
5851927 Method of forming a semiconductor device by DUV resist patterning Paul Cox, Samuel J. Wright, Judith Sobresky 1998-12-22