Issued Patents All Time
Showing 1–25 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8638638 | Delay locked loop implementation in a synchronous dynamic random access memory | Peter B. Gillingham, Graham Allan | 2014-01-28 |
| 8441878 | Embedded memory databus architecture | — | 2013-05-14 |
| 8369182 | Delay locked loop implementation in a synchronous dynamic random access memory | Peter B. Gillingham, Graham Allan | 2013-02-05 |
| 8218386 | Embedded memory databus architecture | — | 2012-07-10 |
| 7859930 | Embedded memory databus architecture | — | 2010-12-28 |
| 7636880 | Error correction scheme for memory | — | 2009-12-22 |
| 7609573 | Embedded memory databus architecture | — | 2009-10-27 |
| 7599246 | Delay locked loop implementation in a synchronous dynamic random access memory | Peter B. Gillingham, Graham Allan | 2009-10-06 |
| 7486580 | Wide databus architecture | — | 2009-02-03 |
| RE40552 | Dynamic random access memory using imperfect isolating transistors | Peter B. Gillingham, Robert Harland, Masami Mitsuhashi, Atsushi Wada | 2008-10-28 |
| 7350137 | Method and circuit for error correction in CAM cells | Alan Roth | 2008-03-25 |
| 7266747 | Error correction scheme for memory | — | 2007-09-04 |
| 7095666 | Wide databus architecture | — | 2006-08-22 |
| 7010741 | Method and circuit for error correction in CAM cells | Alan Roth | 2006-03-07 |
| 6992950 | Delay locked loop implementation in a synchronous dynamic random access memory | Peter B. Gillingham, Graham Allan | 2006-01-31 |
| 6980448 | DRAM boosted voltage supply | Peter B. Gillingham, Robert Harland, Valerie L. Lines | 2005-12-27 |
| 6888730 | Content addressable memory cell | Charles Taylor, Curtis Richardson | 2005-05-03 |
| 6888731 | Method and apparatus for replacing defective rows in a semiconductor memory array | Alan Roth, Douglas Perry | 2005-05-03 |
| 6873532 | Content addressable memory cell having improved layout | — | 2005-03-29 |
| 6751111 | High density memory cell | Cormac Michael O'Connell | 2004-06-15 |
| 6661723 | Wide databus architecture | — | 2003-12-09 |
| 6657918 | Delayed locked loop implementation in a synchronous dynamic random access memory | Peter B. Gillingham, Graham Allan | 2003-12-02 |
| 6657919 | Delayed locked loop implementation in a synchronous dynamic random access memory | Peter B. Gillingham, Graham Allan | 2003-12-02 |
| 6614705 | Dynamic random access memory boosted voltage supply | Peter B. Gillingham, Robert Harland, Valerie L. Lines | 2003-09-02 |
| 6580654 | Boosted voltage supply | Peter B. Gillingham, Robert Harland, Valerie L. Lines | 2003-06-17 |