Issued Patents All Time
Showing 76–100 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5022007 | Test signal generator for semiconductor integrated circuit memory and testing method thereof | Kazutami Arimoto, Tsukasa Ooishi, Masaki Tsukude, Kazuyasu Fujishima | 1991-06-04 |
| 5014241 | Dynamic semiconductor memory device having reduced soft error rate | Mikio Asakura, Kazuyasu Fujishima | 1991-05-07 |
| 5012447 | Bit line structure for a dynamic type semiconductor memory device | Kazuyasu Fujishima | 1991-04-30 |
| 4980310 | Method of making a trench dram cell | Kazuyasu Fujishima | 1990-12-25 |
| 4977542 | Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout | Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Masaki Tsukude | 1990-12-11 |
| 4972380 | Decoding circuit for functional block | Hideto Hidaka, Kazuyasu Fujishima | 1990-11-20 |
| 4953164 | Cache memory system having error correcting circuit | Mikio Asakura, Kazuyasu Fujishima | 1990-08-28 |
| 4924560 | Stretchable slide fastener | Mitsuo Horikawa, Noritaka Tsubata | 1990-05-15 |
| 4926385 | Semiconductor memory device with cache memory addressable by block within each column | Kazuyasu Fujishima, Hideto Hidaka, Mikio Asakura | 1990-05-15 |
| 4918692 | Automated error detection for multiple block memory array chip and correction thereof | Hideto Hidaka, Kazuyasu Fujishima | 1990-04-17 |
| 4914630 | Refresh arrangement in a block divided memory including a plurality of shift registers | Kazuyasu Fujishima, Hideto Hidaka | 1990-04-03 |
| 4914632 | Semiconductor devices having redundancy circuitry and operating method therefor | Kazuyasu Fujishima, Mikio Asakura | 1990-04-03 |
| 4890261 | Variable word length circuit of semiconductor memory | Hideto Hidaka, Kazuyasu Fujishima | 1989-12-26 |
| 4887136 | Semiconductor memory device and the method for manufacturing the same | Kazuyasu Fujishima | 1989-12-12 |
| 4873669 | Random access memory device operable in a normal mode and in a test mode | Kiyohiro Furutani, Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto | 1989-10-10 |
| 4858447 | Warp-knit tape for hook-and-loop fasteners | — | 1989-08-22 |
| 4855953 | Semiconductor memory device having stacked memory capacitors and method for manufacturing the same | Katsuhiro Tsukamoto, Masahiro Shimizu, Kazuyasu Fujishima | 1989-08-08 |
| 4849938 | Semiconductor memory device | Kiyohiro Furutani, Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto | 1989-07-18 |
| 4838044 | Warp-knit tape for hook-and-loop fasteners | Mitsutoshi Ishihara | 1989-06-13 |
| 4833518 | Semiconductor memory device having improved interconnection structure of memory cell array | Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto, Kiyohiro Furutani | 1989-05-23 |
| 4833653 | Dynamic random access memory having selectively activated subarrays | Koichiro Mashiko, Kazutami Arimoto, Kiyohiro Furutani, Noriaki Matsumoto | 1989-05-23 |
| 4833645 | Semiconductor memory device having improved resistance to alpha particle induced soft errors | Kazuyasu Fujishima | 1989-05-23 |
| 4817056 | Semiconductor memory device | Kiyohiro Furutani, Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto | 1989-03-28 |
| 4811304 | MDS decoder circuit with high voltage suppression of a decoupling transistor | Hideshi Miyatake, Kazuyasu Fujishima | 1989-03-07 |
| 4797001 | Substrate bias generator for use in dynamic random access memory | Noriaki Matsumoto, Koichiro Mashiko, Kazutami Arimoto, Kiyohiro Furutani | 1989-01-10 |