Issued Patents All Time
Showing 51–75 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5416734 | Bit line structure for semiconductor memory device | Hideto Hidaka, Kazuyasu Fujishima | 1995-05-16 |
| 5412380 | Electronic crosspoint switching device operating at a high signal transmission rate | Harufusa Kondoh, Hiromi Notani, Isamu Hayashi | 1995-05-02 |
| 5373712 | Warp-knit cloth for surface fastener | Toru Yamamoto, Mitsutoshi Ishihara | 1994-12-20 |
| 5375088 | Random access memory with plurality of amplifier groups | Kiyohiro Furutani, Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto | 1994-12-20 |
| 5371714 | Method and apparatus for driving word line in block access memory | Kazuyasu Fujishima, Hideto Hidaka | 1994-12-06 |
| 5353427 | Semiconductor memory device for simple cache system with selective coupling of bit line pairs | Kazuyasu Fujishima, Mikio Asakura | 1994-10-04 |
| 5347270 | Method of testing switches and switching circuit | Harufusa Kondoh, Isamu Hayashi, Hiromi Notani | 1994-09-13 |
| 5293598 | Random access memory with a plurality of amplifier groups | Kiyohiro Furutani, Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto | 1994-03-08 |
| 5289417 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima | 1994-02-22 |
| 5280443 | Bit line structure for semiconductor memory device | Hideto Hidaka, Kazuyasu Fujishima | 1994-01-18 |
| 5267214 | Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor | Kazuyasu Fujishima, Kazutami Arimoto, Tsukasa Ooishi, Masaki Tsukude | 1993-11-30 |
| 5250458 | Method for manufacturing semiconductor memory device having stacked memory capacitors | Katsuhiro Tsukamoto, Masahiro Shimizu, Kazuyasu Fujishima | 1993-10-05 |
| 5226147 | Semiconductor memory device for simple cache system | Kazuyasu Fujishima, Mikio Asakura | 1993-07-06 |
| 5226139 | Semiconductor memory device with a built-in cache memory and operating method thereof | Kazuyasu Fujishima, Hideto Hidaka, Mikio Asakura | 1993-07-06 |
| 5222047 | Method and apparatus for driving word line in block access memory | Kazuyasu Fujishima, Hideto Hidaka | 1993-06-22 |
| 5214601 | Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers | Hideto Hidaka, Kazuyasu Fujishima | 1993-05-25 |
| 5185744 | Semiconductor memory device with test circuit | Kazutami Arimoto, Kazuyasu Fujishima, Tsukasa Ooishi, Masaki Tsukude | 1993-02-09 |
| 5184327 | Semiconductor memory device having on-chip test circuit and method for testing the same | Kazutami Arimoto, Tsukasa Ooishi, Masaki Tsukude, Kazuyasu Fujishima | 1993-02-02 |
| 5179687 | Semiconductor memory device containing a cache and an operation method thereof | Hideto Hidaka, Kazuyasu Fujishima, Mikio Asakura | 1993-01-12 |
| 5136543 | Data descrambling in semiconductor memory device | Kazuyasu Fujishima, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi | 1992-08-04 |
| 5132930 | CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines | Kiyohiro Furutani, Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto | 1992-07-21 |
| 5103426 | Decoding circuit and method for functional block selection | Hideto Hidaka, Kazuyasu Fujishima | 1992-04-07 |
| 5088063 | Semiconductor memory device having on-chip test circuit | Kazutami Arimoto, Tsukasa Ooishi, Masaki Tsukude, Kazuyasu Fujishima | 1992-02-11 |
| 5060230 | On chip semiconductor memory arbitrary pattern, parallel test apparatus and method | Kazutami Arimoto, Kazuyasu Fujishima, Tsukasa Ooishi, Masaki Tsukude | 1991-10-22 |
| 5030586 | Method for manufacturing semiconductor memory device having improved resistance to .alpha. particle induced soft errors | Kazuyasu Fujishima | 1991-07-09 |