Issued Patents All Time
Showing 76–90 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4984210 | Semiconductor memory device improved for externally designating operation mode | Masaki Kumanoya, Katsumi Dosaka, Takahiro Komatsu, Youichi Tobita | 1991-01-08 |
| 4961167 | Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein | Masaki Kumanoya, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue | 1990-10-02 |
| 4961007 | Substrate bias potential generator of a semiconductor integrated circuit device and a generating method therefor | Masaki Kumanoya, Katsumi Dosaka, Takahiro Komatsu, Youichi Tobita | 1990-10-02 |
| 4954992 | Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor | Masaki Kumanoya, Hirofumi Shinohara, Katsumi Dosaka, Takahiro Komatsu, Hiroyuki Yamasaki | 1990-09-04 |
| 4943960 | Self-refreshing of dynamic random access memory device and operating method therefor | Takahiro Komatsu, Masaki Kumanoya, Katsumi Dosaka | 1990-07-24 |
| 4933907 | Dynamic random access memory device and operating method therefor | Masaki Kumanoya, Katsumi Dosaka, Hiroyuki Yamasaki, Takahiro Komatsu, Yoichi Tobita | 1990-06-12 |
| 4907199 | Dynamic semiconductor memory device and method for controllig the precharge/refresh and access modes thereof | Katsumi Dosaka, Masaki Kumanoya, Hiroyuki Yamasaki, Takahiro Komatsu | 1990-03-06 |
| 4899313 | Semiconductor memory device with an improved multi-bit test mode | Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka | 1990-02-06 |
| 4896297 | Circuit for generating a boosted signal for a word line | Hideshi Miyatake, Kazuyasu Fujishima, Masaki Kumanoya, Hideto Hidaka, Katsumi Dosaka | 1990-01-23 |
| 4843596 | Semiconductor memory device with address transition detection and timing control | Hideshi Miyatake, Masaki Kumanoya, Hideto Hidaka, Katsumi Dosaka, Hiroyuki Yamasaki +3 more | 1989-06-27 |
| 4837747 | Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block | Katsumi Dosaka, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Hiroyuki Yamasaki +3 more | 1989-06-06 |
| 4823322 | Dynamic random access memory device having an improved timing arrangement | Hideshi Miyatake, Masaki Kumanoya, Hideto Hidaka, Katsumi Dosaka, Hiroyuki Yamasaki +3 more | 1989-04-18 |
| 4809230 | Semiconductor memory device with active pull up | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Katsumi Dosaka | 1989-02-28 |
| 4736343 | Dynamic RAM with active pull-up circuit | Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka | 1988-04-05 |
| 4734890 | Dynamic RAM having full-sized dummy cell | Hideshi Miyatake, Kazuyasu Fujishima, Masaki Kumanoya, Hideto Hidaka, Katsumi Dosaka | 1988-03-29 |