Issued Patents All Time
Showing 51–75 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5592434 | Synchronous semiconductor memory device | Hisashi Iwamoto, Katsumi Dosaka, Yasumitsu Murai | 1997-01-07 |
| 5587950 | Test circuit in clock synchronous semiconductor memory device | Seiji Sawada | 1996-12-24 |
| 5583813 | Semiconductor memory device | Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto +4 more | 1996-12-10 |
| 5559750 | Semiconductor memory device | Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto +4 more | 1996-09-24 |
| 5544121 | Semiconductor memory device | Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto +4 more | 1996-08-06 |
| 5530379 | Output buffer circuit that can be shared by a plurality of interfaces and a semiconductor device using the same | Takashi Araki, Hisashi Iwamoto | 1996-06-25 |
| 5517462 | Synchronous type semiconductor memory device operating in synchronization with an external clock signal | Hisashi Iwamoto, Yasumitsu Murai, Naoya Watanabe, Seiji Sawada | 1996-05-14 |
| 5511029 | Test circuit in clock synchronous semiconductor memory device | Seiji Sawada | 1996-04-23 |
| 5473178 | Semiconductor memory cell for holding data with small power consumption | — | 1995-12-05 |
| 5471430 | Test circuit for refresh counter of clock synchronous type semiconductor memory device | Seiji Sawada | 1995-11-28 |
| 5469099 | Power-on reset signal generator and operating method thereof | — | 1995-11-21 |
| 5404338 | Synchronous type semiconductor memory device operating in synchronization with an external clock signal | Yasumitsu Murai, Hisashi Iwamoto, Naoya Watanabe, Seiji Sawada | 1995-04-04 |
| 5384745 | Synchronous semiconductor memory device | Takayuki Miyamoto, Takeshi Kajimoto, Hisashi Iwamoto | 1995-01-24 |
| 5359215 | Semiconductor memory cell for holding data with small power consumption | — | 1994-10-25 |
| 5289431 | Semiconductor memory device divided into blocks and operable to read and write data through different data lines and operation method of the same | — | 1994-02-22 |
| 5270977 | Dynamic random access memory device capable of performing test mode operation and method of operating such memory device | Hisashi Iwamoto, Masaki Kumanoya, Katsumi Dosaka, Akira Yamazaki | 1993-12-14 |
| RE34463 | Semiconductor memory device with active pull up | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Katsumi Dosaka | 1993-11-30 |
| 5208778 | Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof | Masaki Kumanoya, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue | 1993-05-04 |
| 5184321 | Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement | Masaki Kumanoya, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue | 1993-02-02 |
| 5151614 | Circuit having charge compensation and an operation method of the same | Akira Yamazaki, Masaki Kumanoya, Katsumi Dosaka | 1992-09-29 |
| 5097440 | Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement | Masaki Kumanoya, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue | 1992-03-17 |
| 5079748 | Dynamic random access memory with read-write signal of shortened duration | Hideshi Miyatake, Masaki Kumanoya, Hideto Hidaka, Hiroyuki Yamasaki, Yuto Ikeda | 1992-01-07 |
| 5014246 | Semiconductor memory device having shared sense amplifier and operating method thereof | Takahiro Komatsu, Masaki Kumanoya, Katsumi Dosaka, Yoshinori Inoue | 1991-05-07 |
| 5010259 | Voltage boosting circuit and operating method thereof | Yoshinori Inoue, Masaki Kumanoya, Takahiro Komatsu, Katsumi Dosaka | 1991-04-23 |
| 4989183 | Semiconductor memory device improved for externally designating operation mode | Masaki Kumanoya, Katsumi Dosaka, Takahiro Komatsu, Youichi Tobita | 1991-01-29 |