Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5226149 | Self-testing microprocessor with microinstruction substitution | Yuichi Saito | 1993-07-06 |
| 5218711 | Microprocessor having program counter registers for its coprocessors | — | 1993-06-08 |
| 5210864 | Pipelined microprocessor with instruction execution control unit which receives instructions from separate path in test mode for testing instruction execution pipeline | — | 1993-05-11 |
| 5193205 | Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address | Masahito Matsuo | 1993-03-09 |
| 5193156 | Data processor with pipeline which disables exception processing for non-taken branches | Masahito Matuo | 1993-03-09 |
| 5148529 | Pipelined multi-stage data processor including an operand bypass mechanism | Tatsuya Ueda | 1992-09-15 |
| 5140684 | Access privilege-checking apparatus and method | Ken Sakamura | 1992-08-18 |
| 5132898 | System for processing data having different formats | Ken Sakamura | 1992-07-21 |
| 5129068 | Operand address calculation in a pipeline processor by decomposing the operand specifier into sequential step codes | Tetsuya Watanabe | 1992-07-07 |
| 5122693 | Clock system implementing divided power supply wiring | Nobuhiko Honda, Yukihiko Shimazu | 1992-06-16 |
| 5091853 | Chained addressing mode pipelined processor which merges separately decoded parts of a multiple operation instruction | Tetsuya Watanabe | 1992-02-25 |
| 4974158 | Multiple sequentially transferrable stackpointers in a data processor in a pipelining system | Yukari Watanabe, Masahito Matsuo, Yuichi Saito, Toru Shimizu | 1990-11-27 |
| 4945511 | Improved pipelined processor with two stage decoder for exchanging register values for similar operand instructions | Fujio Itomitsu | 1990-07-31 |
| 4912634 | Data processing system using multiplexer for variable sequencing based on instruction type of instructions prefetched for parallel processing | Tadayoshi Nakano | 1990-03-27 |
| 4907147 | Pipelined data processing system with register indirect addressing | Yuuichi Saito | 1990-03-06 |
| 4858104 | Preceding instruction address based branch prediction in a pipelined processor | Masahito Matsuo | 1989-08-15 |
| 4847753 | Pipelined computer | Masahito Matsuo | 1989-07-11 |
| 4807176 | Manchester type carry propagation circuit | Akira Yamada, Hiromasa Nakagawa | 1989-02-21 |
| 4802112 | MOS transistor circuit | Tatsuya Ueda | 1989-01-31 |
| 4796175 | Instruction fetching in data processing apparatus | Masahito Matsuo | 1989-01-03 |
| 4755968 | Buffer memory device controlled by a least recently used method | Yoshihiro Seguchi | 1988-07-05 |
| 4670666 | MOS transistor circuit for shared precharging of bus lines | — | 1987-06-02 |