Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7457996 | Semiconductor integrated circuit capable of testing with small scale circuit configuration | Soichi Kobayashi, Yoshiaki Yamazaki | 2008-11-25 |
| 6748464 | Semiconductor device comprising CPU and peripheral circuit wherein control unit performs wait cycle control that makes peripheral circuit wait a predetermined time before responding to CPU | Yasufumi Mori, Teruyuki Itou | 2004-06-08 |
| 6721897 | Bus control circuit effecting timing control using cycle registers for respective cycles holding signal levels corresponding to bus control signals that are output by arrangement of signal level | Akira Oizumi, Norio Masui | 2004-04-13 |
| 6711692 | Data processing unit including central unit and peripheral unit driven by separate power supplies | Hiromi Maeda, Masayuki Hata | 2004-03-23 |
| 6504186 | Semiconductor device having a library of standard cells and method of designing the same | Toshiki Kanamoto, Yoshihide Ajioka, Hideyuki HAMADA | 2003-01-07 |
| 6388277 | Auto placement and routing device and semiconductor integrated circuit | Hiroyuki Kobayashi | 2002-05-14 |
| 6339821 | Data processor capable of handling an increased number of operation codes | Hiromi Maeda, Akihiko Ishida | 2002-01-15 |
| 6253364 | Automatic placement and routing device | Genichi Tanaka | 2001-06-26 |
| 6009254 | Processing apparatus having reduced bus lengths between operating units and register file | Hiroyuki Kobayashi | 1999-12-28 |
| 5969553 | Digital delay circuit and digital PLL circuit with first and second delay units | Toshio Kishi | 1999-10-19 |
| 5936455 | MOS integrated circuit with low power consumption | Souichi Kobayashi, Toshio Kishi | 1999-08-10 |
| 5801559 | Clock generating circuit, PLL circuit, semiconductor device, and methods for designing and making the clock generating circuit | Katsunori Sawai | 1998-09-01 |
| 5787310 | Microcomputer | Toru Shimizu, Katsunori Sawai, Masaki Kumanoya, Katsumi Dosaka | 1998-07-28 |
| 5551045 | Microprocessor with reset execution from an arbitrary address | Kohji Kawamoto, Toshiki Fujiyama | 1996-08-27 |
| 5497109 | Integrated circuit with reduced clock skew | Nubuhiko Honda, Toyohiko Yoshida | 1996-03-05 |
| 5495433 | Data processing circuit | Yukari Takata | 1996-02-27 |
| 5376842 | Integrated circuit with reduced clock skew and divided power supply lines | Nobuhiko Honoa, Toyohiko Yoshida | 1994-12-27 |
| 5361371 | Microprocessor with reset execution from an arbitrary address | Kohji Kawamoto, Toshiki Fujiyama | 1994-11-01 |
| 5278466 | Integrated circuit with reduced clock skew | Nobuniko Honoa, Toyohiko Yoshida | 1994-01-11 |
| 5195055 | Serial data input circuit for the shifting-in of variable length data | Hisako Mizuoka | 1993-03-16 |
| 5140546 | Adder circuit apparatus | Kazuyuki Ishikawa, Toshiki Fujiyama | 1992-08-18 |
| 5122693 | Clock system implementing divided power supply wiring | Nobuhiko Honda, Toyohiko Yoshida | 1992-06-16 |
| 5051997 | Semiconductor integrated circuit with self-test function | Narumi Sakashita | 1991-09-24 |
| 5034887 | Microprocessor with Harvard Architecture | Ikuo Yasui | 1991-07-23 |
| 4947411 | Programmable clock frequency divider | Taketora Shiraishi | 1990-08-07 |