Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7487338 | Data processor for modifying and executing operation of instruction code according to the indication of other instruction code | — | 2009-02-03 |
| 7010677 | Data processor speeding up repeat processing by inhibiting remaining instructions after a break in a repeat block | — | 2006-03-07 |
| 6925548 | Data processor assigning the same operation code to multiple operations | — | 2005-08-02 |
| RE38679 | Data processor and method of processing data | Toyohiko Yoshida | 2004-12-28 |
| 6484253 | Data processor | — | 2002-11-19 |
| 6408385 | Data processor | Toyohiko Yoshida | 2002-06-18 |
| 6178492 | Data processor capable of executing two instructions having operand interference at high speed in parallel | — | 2001-01-23 |
| 6151673 | Data processor | Toyohiko Yoshida | 2000-11-21 |
| 6131158 | Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel | Toru Shimizu, Toyohiko Yoshida | 2000-10-10 |
| 6112289 | Data processor | — | 2000-08-29 |
| 6058471 | Data processing system capable of executing groups of instructions in parallel | Toru Shimizu, Toyohiko Yoshida | 2000-05-02 |
| 5978904 | Data processor | Toyohiko Yoshida | 1999-11-02 |
| 5924114 | Circular buffer with two different step sizes | Toshiyuki Maruyama | 1999-07-13 |
| 5901301 | Data processor and method of processing data | Toyohiko Yoshida | 1999-05-04 |
| 5848268 | Data processor with branch target address generating unit | — | 1998-12-08 |
| 5812809 | Data processing system capable of execution of plural instructions in parallel | Toru Shimizu, Toyohiko Yoshida | 1998-09-22 |
| 5745723 | Data processing system capable of execution of plural instructions in parallel | Toru Shimizu, Toyohiko Yoshida | 1998-04-28 |
| 5701449 | Data processor | Toyohiko Yoshida | 1997-12-23 |
| 5649145 | Data processor processing a jump instruction | Toyohiko Yoshida | 1997-07-15 |
| 5617550 | Data processor generating jump target address of a jump instruction in parallel with decoding of the instruction | Toyohiko Yoshida | 1997-04-01 |
| 5615349 | Data processing system capable of execution of plural instructions in parallel | Toru Shimizu, Toyohiko Yoshida | 1997-03-25 |
| 5592637 | Data processor processing a jump instruction | — | 1997-01-07 |
| 5590296 | Data processor processing a jump instruction | — | 1996-12-31 |
| 5566307 | Multiple sequentially transferrable stackpointers in a data processor in a pipelining system | Yukari Watanabe, Toyohiko Yoshida, Yuichi Saito, Toru Shimizu | 1996-10-15 |
| 5526498 | Pipeline processor, with a return address stack and two stack pointers, for storing pre-return processed addresses | Toyohiko Yoshida | 1996-06-11 |