Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5485587 | Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction | Toyohiko Yoshida | 1996-01-16 |
| 5461715 | Data processor capable of execution of plural instructions in parallel | Toru Shimizu, Toyohiko Yoshida | 1995-10-24 |
| 5453927 | Data processor for processing branch instructions | — | 1995-09-26 |
| 5386580 | Data processor | Toyohiko Yoshida | 1995-01-31 |
| 5361338 | Pipelined system for decomposing instruction into two decoding parts and either concurrently generating two operands addresses of merging decomposing decoding codes based upon the second operand | Souichi Kobayashi | 1994-11-01 |
| 5355459 | Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address | Toyohiko Yoshida | 1994-10-11 |
| 5349681 | Bit searching circuit and data processor including the same | Toyohiko Yoshida | 1994-09-20 |
| 5321821 | System for processing parameters in instructions of different format to execute the instructions using same microinstructions | Fujio Itomitsu | 1994-06-14 |
| 5313644 | System having status update controller for determining which one of parallel operation results of execution units is allowed to set conditions of shared processor status word | Toru Shimizu | 1994-05-17 |
| 5220656 | System for selecting control parameter for microinstruction execution unit using parameters and parameter selection signal decoded from instruction | Fujio Itomitsu | 1993-06-15 |
| 5193205 | Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address | Toyohiko Yoshida | 1993-03-09 |
| 4974158 | Multiple sequentially transferrable stackpointers in a data processor in a pipelining system | Yukari Watanabe, Toyohiko Yoshida, Yuichi Saito, Toru Shimizu | 1990-11-27 |
| 4974154 | Computer with instruction prefetch queue retreat unit | — | 1990-11-27 |
| 4858104 | Preceding instruction address based branch prediction in a pipelined processor | Toyohiko Yoshida | 1989-08-15 |
| 4847753 | Pipelined computer | Toyohiko Yoshida | 1989-07-11 |
| 4796175 | Instruction fetching in data processing apparatus | Toyohiko Yoshida | 1989-01-03 |