Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5522053 | Branch target and next instruction address calculation in a pipeline processor | Masahito Matuo | 1996-05-28 |
| 5519881 | Priority encoder for accessing multiple registers simultaneously and a data processing system which uses it | Yukari Takata | 1996-05-21 |
| 5502827 | Pipelined data processor for floating point and integer operation with exception handling | — | 1996-03-26 |
| 5497109 | Integrated circuit with reduced clock skew | Nubuhiko Honda, Yukihiko Shimazu | 1996-03-05 |
| 5497468 | Data processor that utilizes full data width when processing a string operation | Kunio Tani, Yukari Takata | 1996-03-05 |
| 5485587 | Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction | Masahito Matsuo | 1996-01-16 |
| 5481734 | Data processor having 2n bits width data bus for context switching function | — | 1996-01-02 |
| 5475852 | Microprocessor implementing single-step or sequential microcode execution while in test mode | Yuichi Saito | 1995-12-12 |
| 5465376 | Microprocessor, coprocessor and data processing system using them | — | 1995-11-07 |
| 5461715 | Data processor capable of execution of plural instructions in parallel | Masahito Matsuo, Toru Shimizu | 1995-10-24 |
| 5440704 | Data processor having branch predicting function | Fujio Itomitsu | 1995-08-08 |
| 5440757 | Data processor having multistage store buffer for processing exceptions | — | 1995-08-08 |
| 5434988 | Data processor implementing a two's complement addressing technique | Ken Sakamura | 1995-07-18 |
| 5421029 | Multiprocessor including system for pipeline processing of multi-functional instructions | — | 1995-05-30 |
| 5396610 | Register address specifying circuit for simultaneously accessing two registers | Yukari Takata | 1995-03-07 |
| 5390307 | Apparatus for a multi-data store or load instruction for transferring multiple contiguous storage locations in one transfer operation | — | 1995-02-14 |
| 5386580 | Data processor | Masahito Matsuo | 1995-01-31 |
| 5376842 | Integrated circuit with reduced clock skew and divided power supply lines | Nobuhiko Honoa, Yukihiko Shimazu | 1994-12-27 |
| 5355459 | Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address | Masahito Matsuo | 1994-10-11 |
| 5349681 | Bit searching circuit and data processor including the same | Masahito Matsuo | 1994-09-20 |
| 5327542 | Data processor implementing a two's complement addressing technique | Ken Sakamura | 1994-07-05 |
| 5300811 | Integrated circuit device and microprocessor constituted thereby | Katsunori Suzuki | 1994-04-05 |
| 5278466 | Integrated circuit with reduced clock skew | Nobuniko Honoa, Yukihiko Shimazu | 1994-01-11 |
| 5239633 | Data processor executing memory indirect addressing and register indirect addressing | Fumihiko Terayama, Yuichi Saitou | 1993-08-24 |
| 5228131 | Data processor with selectively enabled and disabled branch prediction operation | Tatsuya Ueda | 1993-07-13 |