Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5475638 | Static random access memory device having a single bit line configuration | Kenji Anami, Toshihiko Hirose, Shuji Murakami, Kojiro Yuzuriha | 1995-12-12 |
| 5418923 | Circuit for prioritizing outputs of an associative memory with parallel inhibition paths and a compact architecture | Masaaki Mihara, Takeshi Hamamoto | 1995-05-23 |
| 5404329 | Boosting circuit improved to operate in a wider range of power supply voltage, and a semiconductor memory and a semiconductor integrated circuit device using the same | Yoshikazu Morooka | 1995-04-04 |
| 5388066 | Content addressable memory device and a method of disabling a coincidence word thereof | Takeshi Hamamoto, Masaaki Mihara | 1995-02-07 |
| 5367493 | Dynamic type semiconductor memory device having reduced peak current during refresh mode and method of operating the same | — | 1994-11-22 |
| 5319589 | Dynamic content addressable memory device and a method of operating thereof | Masaaki Mihara, Takeshi Hamamoto, Hideyuki Ozaki | 1994-06-07 |
| 5228000 | Test circuit of semiconductor memory device | — | 1993-07-13 |
| 5208474 | Input circuit of a semiconductor device | Hiroshi Miyamoto, Michihiro Yamada | 1993-05-04 |
| 5158899 | Method of manufacturing input circuit of semiconductor device | — | 1992-10-27 |
| 5146300 | Semiconductor integrated circuit device having improved stacked capacitor and manufacturing method therefor | Takeshi Hamamoto, Toshifumi Kobayashi, Masaaki Mihara | 1992-09-08 |
| 5126968 | Content addressable semiconductor memory device and operating method therefor | Takeshi Hamamoto, Toshifumi Kobayashi, Masaaki Mihara | 1992-06-30 |
| 5083188 | Integrated circuit having superconductive wirings | — | 1992-01-21 |
| 5016220 | Semiconductor memory device with logic level responsive testing circuit and method therefor | — | 1991-05-14 |
| 4984054 | Electric fuse for a redundancy circuit | Michihiro Yamada, Hiroshi Miyamoto, Shigeru Mori | 1991-01-08 |
| 4974053 | Semiconductor device for multiple packaging configurations | Mitsuya Kinoshita, Hiroshi Miyamoto | 1990-11-27 |
| 4904885 | Substrate bias circuit having substrate bias voltage clamp and operating method therefor | Michihiro Yamada, Hiroshi Miyamoto, Shigeru Mori, Tetsuya Aono | 1990-02-27 |
| 4870620 | Dynamic random access memory device with internal refresh | Hiroshi Miyamoto, Michihiro Yamada, Shigeru Mori, Tetsuya Aono | 1989-09-26 |
| 4788455 | CMOS reference voltage generator employing separate reference circuits for each output transistor | Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada, Kazutami Arimoto | 1988-11-29 |
| 4780850 | CMOS dynamic random access memory | Hiroshi Miyamoto, Shigeru Mori, Michihiro Yamada | 1988-10-25 |
| 4734889 | Semiconductor memory | Koichiro Mashiko, Yoshikazu Morooka, Yuto Ikeda | 1988-03-29 |