Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6088286 | Word line non-boosted dynamic semiconductor memory device | Kazutami Arimoto | 2000-07-11 |
| 6084386 | Voltage generation circuit capable of supplying stable power supply voltage to load operating in response to timing signal | Mitsue Takahashi, Mitsuya Kinoshita | 2000-07-04 |
| 6064275 | Internal voltage generation circuit having ring oscillator whose frequency changes inversely with power supply voltage | — | 2000-05-16 |
| 6064557 | Semiconductor device structured to be less susceptible to power supply noise | Kyoji Yamasaki, Mikio Asakura | 2000-05-16 |
| 6061808 | Semiconductor memory device having a multibit test mode | Mikio Asakura, Takashi Ito | 2000-05-09 |
| 6003148 | Semiconductor memory device allowing repair of a defective memory cell with a redundant circuit in a multibit test mode | Mikio Asakura, Takashi Ito | 1999-12-14 |
| 5982162 | Internal voltage generation circuit that down-converts external power supply voltage and semiconductor device generating internal power supply voltage on the basis of reference voltage | — | 1999-11-09 |
| 5978299 | Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation | Kyoji Yamasaki, Mikio Asakura | 1999-11-02 |
| 5973554 | Semiconductor device structured to be less susceptible to power supply noise | Kyoji Yamasaki, Mikio Asakura | 1999-10-26 |
| 5917766 | Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably | Takaharu Tsuji, Mikio Asakura, Koji Tanaka | 1999-06-29 |
| 5875145 | Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation | Kyoji Yamasaki, Mikio Asakura | 1999-02-23 |
| 5838047 | CMOS substrate biasing for threshold voltage control | Kazutami Arimoto | 1998-11-17 |
| 5812492 | Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal | Takaharu Tsuji, Mikio Asakura | 1998-09-22 |
| 5801451 | Semiconductor device including a plurality of input buffer circuits receiving the same control signal | — | 1998-09-01 |
| 5789808 | Semiconductor device structured to be less susceptible to power supply noise | Kyoji Yamasaki, Mikio Asakura | 1998-08-04 |
| 5783957 | Differential amplifier circuit, CMOS inverter, demodulator circuit for pulse-width modulation, and sampling circuit | — | 1998-07-21 |
| 5744998 | Internal voltage detecting circuit having superior responsibility | Takashi Ito, Takaharu Tsuji | 1998-04-28 |
| 5732034 | Semiconductor memory device having an address key circuit for reducing power consumption | Mikio Asakura, Takashi Ito | 1998-03-24 |
| 5691955 | Synchronous semiconductor memory device operating in synchronization with external clock signal | — | 1997-11-25 |
| 5663912 | Semiconductor memory device | — | 1997-09-02 |
| 5640363 | Semiconductor memory device | Kiyohiro Furutani, Makiko Aoki | 1997-06-17 |
| 5621343 | Demodulator circuit which demodulates pulse width modulated signals used in a semiconductor integrated circuit | — | 1997-04-15 |
| 5487043 | Semiconductor memory device having equalization signal generating circuit | Kiyohiro Furutani, Makiko Aoki | 1996-01-23 |
| 5481497 | Semiconductor memory device providing external output data signal in accordance with states of true and complementary read buses | Hiroshi Miyamoto, Yoshikazu Morooka, Kiyohiro Furutani, Makiko Aoki | 1996-01-02 |
| 5469402 | Buffer circuit of a semiconductor memory device | Kei Hamade, Yoshikazu Morooka | 1995-11-21 |