Issued Patents All Time
Showing 101–123 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4954992 | Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor | Masaki Kumanoya, Hirofumi Shinohara, Yasuhiro Konishi, Takahiro Komatsu, Hiroyuki Yamasaki | 1990-09-04 |
| 4943960 | Self-refreshing of dynamic random access memory device and operating method therefor | Takahiro Komatsu, Masaki Kumanoya, Yasuhiro Konishi | 1990-07-24 |
| 4933907 | Dynamic random access memory device and operating method therefor | Masaki Kumanoya, Yasuhiro Konishi, Hiroyuki Yamasaki, Takahiro Komatsu, Yoichi Tobita | 1990-06-12 |
| 4907199 | Dynamic semiconductor memory device and method for controllig the precharge/refresh and access modes thereof | Masaki Kumanoya, Yasuhiro Konishi, Hiroyuki Yamasaki, Takahiro Komatsu | 1990-03-06 |
| 4903238 | Semiconductor memory device with improved immunity to supply voltage fluctuations | Hideshi Miyatake, Masaki Kumanoya | 1990-02-20 |
| 4903268 | Semiconductor memory device having on-chip error check and correction functions | Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Tsutomu Yoshihara | 1990-02-20 |
| 4899313 | Semiconductor memory device with an improved multi-bit test mode | Masaki Kumanoya, Hideshi Miyatake, Yasuhiro Konishi | 1990-02-06 |
| 4896297 | Circuit for generating a boosted signal for a word line | Hideshi Miyatake, Kazuyasu Fujishima, Masaki Kumanoya, Hideto Hidaka, Yasuhiro Konishi | 1990-01-23 |
| 4843596 | Semiconductor memory device with address transition detection and timing control | Hideshi Miyatake, Masaki Kumanoya, Hideto Hidaka, Yasuhiro Konishi, Hiroyuki Yamasaki +3 more | 1989-06-27 |
| 4837747 | Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block | Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Yasuhiro Konishi, Hiroyuki Yamasaki +3 more | 1989-06-06 |
| 4823322 | Dynamic random access memory device having an improved timing arrangement | Hideshi Miyatake, Masaki Kumanoya, Hideto Hidaka, Yasuhiro Konishi, Hiroyuki Yamasaki +3 more | 1989-04-18 |
| 4809230 | Semiconductor memory device with active pull up | Yasuhiro Konishi, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka | 1989-02-28 |
| 4760559 | Semiconductor memory device | Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake | 1988-07-26 |
| 4757476 | Dummy word line driving circuit for a MOS dynamic RAM | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Tsutomu Yoshihara | 1988-07-12 |
| 4736343 | Dynamic RAM with active pull-up circuit | Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Yasuhiro Konishi | 1988-04-05 |
| 4734890 | Dynamic RAM having full-sized dummy cell | Hideshi Miyatake, Kazuyasu Fujishima, Masaki Kumanoya, Hideto Hidaka, Yasuhiro Konishi | 1988-03-29 |
| 4730320 | Semiconductor memory device | Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Tsutomu Yoshihara | 1988-03-08 |
| 4722074 | Semiconductor storage unit with I/O bus precharging and equalization | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Tsutomu Yoshihara | 1988-01-26 |
| 4719597 | Driving circuit for a shared sense amplifier with increased speed clock generation circuit for reading addressed memory cells | Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Hideto Hidaka | 1988-01-12 |
| 4712123 | Dynamic memory device | Hideshi Miyatake, Kazuyasu Fujishima, Tsutomu Yoshihara, Masaki Kumanoya, Hideto Hidaka | 1987-12-08 |
| 4710901 | Driving circuit for a shared sense amplifier | Masaki Kumanoya, Kazuyasu Fujishima | 1987-12-01 |
| 4692901 | Semiconductor memory | Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Hideto Hidaka, Yasumasa Nishimura | 1987-09-08 |
| 4675850 | Semiconductor memory device | Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Hideto Hidaka, Tsutomu Yoshihara | 1987-06-23 |