Issued Patents All Time
Showing 76–100 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5650968 | Semiconductor memory device | Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe +4 more | 1997-07-22 |
| 5629895 | Semiconductor memory device | Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe +4 more | 1997-05-13 |
| 5623454 | Semiconductor memory device | Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe +4 more | 1997-04-22 |
| 5603009 | Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM | Yasuhiro Konishi, Kouji Hayano, Masaki Kumanoya, Akira Yamazaki, Hisashi Iwamoto | 1997-02-11 |
| 5592434 | Synchronous semiconductor memory device | Hisashi Iwamoto, Yasuhiro Konishi, Yasumitsu Murai | 1997-01-07 |
| 5583813 | Semiconductor memory device | Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe +4 more | 1996-12-10 |
| 5559750 | Semiconductor memory device | Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe +4 more | 1996-09-24 |
| 5544121 | Semiconductor memory device | Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe +4 more | 1996-08-06 |
| 5521878 | Clock synchronous semiconductor memory device | Jun Ohtani, Akira Yamazaki | 1996-05-28 |
| 5475268 | Semiconductor device having an alignment mark | Tomoya Kawagoe, Akihisa Oishi, Mitsutaka Niiro | 1995-12-12 |
| 5361223 | Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement | Yoshinori Inoue, Masaki Kumanoya, Takahiro Komatsu | 1994-11-01 |
| 5278789 | Semiconductor memory device with improved buffer for generating internal write designating signal and operating method thereof | Kazunari Inoue | 1994-01-11 |
| 5270977 | Dynamic random access memory device capable of performing test mode operation and method of operating such memory device | Hisashi Iwamoto, Masaki Kumanoya, Yasuhiro Konishi, Akira Yamazaki | 1993-12-14 |
| RE34463 | Semiconductor memory device with active pull up | Yasuhiro Konishi, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka | 1993-11-30 |
| 5208778 | Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof | Masaki Kumanoya, Yasuhiro Konishi, Takahiro Komatsu, Yoshinori Inoue | 1993-05-04 |
| 5184321 | Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement | Yasuhiro Konishi, Masaki Kumanoya, Takahiro Komatsu, Yoshinori Inoue | 1993-02-02 |
| 5151614 | Circuit having charge compensation and an operation method of the same | Akira Yamazaki, Masaki Kumanoya, Yasuhiro Konishi | 1992-09-29 |
| 5097440 | Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement | Yasuhiro Konishi, Masaki Kumanoya, Takahiro Komatsu, Yoshinori Inoue | 1992-03-17 |
| 5014246 | Semiconductor memory device having shared sense amplifier and operating method thereof | Takahiro Komatsu, Masaki Kumanoya, Yasuhiro Konishi, Yoshinori Inoue | 1991-05-07 |
| 5010259 | Voltage boosting circuit and operating method thereof | Yoshinori Inoue, Masaki Kumanoya, Takahiro Komatsu, Yasuhiro Konishi | 1991-04-23 |
| 4989183 | Semiconductor memory device improved for externally designating operation mode | Masaki Kumanoya, Yasuhiro Konishi, Takahiro Komatsu, Youichi Tobita | 1991-01-29 |
| 4984210 | Semiconductor memory device improved for externally designating operation mode | Masaki Kumanoya, Yasuhiro Konishi, Takahiro Komatsu, Youichi Tobita | 1991-01-08 |
| 4984206 | Random access memory with reduced access time in reading operation and operating method thereof | Takahiro Komatsu, Hiroyuki Yamasaki, Yoichi Tobita | 1991-01-08 |
| 4961167 | Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein | Masaki Kumanoya, Yasuhiro Konishi, Takahiro Komatsu, Yoshinori Inoue | 1990-10-02 |
| 4961007 | Substrate bias potential generator of a semiconductor integrated circuit device and a generating method therefor | Masaki Kumanoya, Yasuhiro Konishi, Takahiro Komatsu, Youichi Tobita | 1990-10-02 |