Issued Patents All Time
Showing 26–50 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7277306 | Associative memory capable of searching for data while keeping high data reliability | Hideyuki Noda | 2007-10-02 |
| 7197099 | Delay circuit with timing adjustment function | — | 2007-03-27 |
| 7102954 | Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip | Hideyuki Noda, Kazutami Arimoto, Takeshi Fujino | 2006-09-05 |
| 7092305 | Semiconductor memory device | Naoya Watanabe, Aiko Nishino | 2006-08-15 |
| 7007215 | Test circuit capable of testing embedded memory with reliability | Mitsuya Kinoshita, Tetsushi Tanizaki, Masaru Haraguchi | 2006-02-28 |
| 6888776 | Semiconductor memory device | Naoya Watanabe, Aiko Nishino | 2005-05-03 |
| 6854078 | Multi-bit test circuit | Mitsuya Kinoshita | 2005-02-08 |
| 6779139 | Circuit for reducing test time and semiconductor memory device including the circuit | Masaru Haraguchi, Tetsushi Tanizaki | 2004-08-17 |
| 6768699 | Semiconductor integrated circuit device with embedded synchronous memory precisely operating in synchronization with high speed clock | — | 2004-07-27 |
| 6762967 | Semiconductor memory device having a circuit for fast operation | Tetsushi Tanizaki, Mikio Asakura | 2004-07-13 |
| 6649984 | Logic-merged memory | Hideyuki Noda, Kazutami Arimoto, Takeshi Fujino | 2003-11-18 |
| 6650583 | Test circuit device capable of identifying error in stored data at memory cell level and semiconductor integrated circuit device including the same | Masaru Haraguchi | 2003-11-18 |
| 6646944 | Semiconductor memory device | Hiroki Shimano | 2003-11-11 |
| 6628560 | Dynamic semiconductor memory device with adjustable refresh frequency | — | 2003-09-30 |
| 6614713 | Semiconductor memory device having a circuit for fast operation | Tetsushi Tanizaki, Mikio Asakura | 2003-09-02 |
| 6597599 | Semiconductor memory | Toshinori Morihara, Hiroki Shimano, Kazutami Arimoto | 2003-07-22 |
| 6545921 | Semiconductor memory device allowing spare memory cell to be tested efficiently | Jun Ohtani | 2003-04-08 |
| 6472716 | Semiconductor device with a well wherein a scaling down of the layout is achieved | Futoshi Igaue | 2002-10-29 |
| 6473352 | Semiconductor integrated circuit device having efficiently arranged link program circuitry | Aiko Nishino, Naoya Watanabe | 2002-10-29 |
| 6452859 | Dynamic semiconductor memory device superior in refresh characteristics | Hiroki Shimano, Kazutami Arimoto | 2002-09-17 |
| 6434661 | Synchronous semiconductor memory including register for storing data input and output mode information | Yasuhiro Konishi, Kouji Hayano, Masaki Kumanoya, Akira Yamazaki, Hisashi Iwamoto | 2002-08-13 |
| 6400628 | Semiconductor memory device | Hiroki Shimano, Hiroki Sugano, Kazutami Arimoto | 2002-06-04 |
| 6400625 | Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester | Kazutami Arimoto, Hiroki Shimano | 2002-06-04 |
| 6378102 | Synchronous semiconductor memory device with multi-bank configuration | Naoya Watanabe | 2002-04-23 |
| 6373774 | Semiconductor memory device with bank configuration | Masatoshi Ishikawa | 2002-04-16 |