JT

Joseph B. Tompkins

ML Mindspeed Technologies, Llc.: 6 patents #19 of 197Top 10%
CL Cavium, Llc.: 3 patents #88 of 220Top 40%
CS Conexant Systems: 2 patents #186 of 657Top 30%
Overall (All Time): #417,690 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9680742 Packet output processing Brian FOLSOM, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew John Nicholas Jones +5 more 2017-06-13
9559982 Packet shaping in a network processor Brian FOLSOM, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew John Nicholas Jones +1 more 2017-01-31
9397938 Packet scheduling in a network processor Brian FOLSOM, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew John Nicholas Jones +1 more 2016-07-19
RE42092 Integrated circuit that processes communication packets with a buffer management engine having a pointer cache Daniel J. Lussier, Wilson P. Snyder, II 2011-02-01
7433904 Buffer memory management Bruce Burns, Michael A. Tsukernik, Jamie Mulderig 2008-10-07
7302619 Error correction in a cache memory Duncan M. Fisher 2007-11-27
7099328 Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task Duane E. Galbi, Bruce Burns, Daniel J. Lussier 2006-08-29
7046686 Integrated circuit that processes communication packets with a buffer management engine having a pointer cache Daniel J. Lussier, Wilson P. Snyder, II 2006-05-16
6888830 Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters Wilson Parkhurst SNYDER II, Daniel J. Lussier 2005-05-03
6804239 Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information Daniel J. Lussier, Wilson Parkhurst SNYDER II 2004-10-12
6760337 Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels Wilson P. Snyder, II, Daniel J. Lussier 2004-07-06
6754223 Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processor Daniel J. Lussier, Wilson P. Snyder, II 2004-06-22