Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11157801 | Neural network processing with the neural network model pinned to on-chip memories of hardware nodes | Douglas C. Burger, Jeremy Fowers, Kalin Ovtcharov | 2021-10-26 |
| 11144820 | Hardware node with position-dependent memories for neural network processing | Douglas C. Burger, Jeremy Fowers | 2021-10-12 |
| 11132599 | Multi-function unit for programmable hardware nodes for neural network processing | Douglas C. Burger, Jeremy Fowers | 2021-09-28 |
| 10958717 | Hardware implemented load balancing | Adrian M. Caulfield, Michael Konstantinos Papamichael, Douglas C. Burger, Shlomi Alkalay | 2021-03-23 |
| 10795678 | Matrix vector multiplier with a vector register file comprising a multi-port memory | Jeremy Fowers, Kalin Ovtcharov, Todd Michael Massengill, Ming Liu, Gabriel Leonard Weisz | 2020-10-06 |
| 10791054 | Flow control and congestion management for acceleration components configured to accelerate a service | Adrian M. Caulfield, Michael Konstantinos Papamichael | 2020-09-29 |
| 10691413 | Block floating point computations using reduced bit-width vectors | Daniel Lo, Douglas C. Burger | 2020-06-23 |
| 10579334 | Block floating point computations using shared exponents | Daniel Lo | 2020-03-03 |
| 10566076 | Customized integrated circuit for serial comparison of nucleotide sequences | Daniel Lo, Kalin Ovtcharov, Ravindra Pandya, David E. Heckerman | 2020-02-18 |
| 10540588 | Deep neural network processing on hardware accelerators with stacked memory | Douglas C. Burger, Derek Chiou, Andrew R. Putnam | 2020-01-21 |
| 10528119 | Dynamic power routing to hardware accelerators | Andrew R. Putnam, Douglas C. Burger, Stephen F. Heil, Adrian M. Caulfield | 2020-01-07 |
| 10467324 | Data packing techniques for hard-wired multiplier circuits | Jeremy Fowers, Shlomo Alkalay | 2019-11-05 |
| 10452971 | Deep neural network partitioning on servers | Karin Strauss, Kalin Ovtcharov, Joo Young Kim, Olatunji Ruwase | 2019-10-22 |
| 10452995 | Machine learning classification on hardware accelerators with stacked memory | Douglas C. Burger, Derek Chiou, Andrew R. Putnam | 2019-10-22 |
| 10455061 | Lightweight transport protocol | Adrian M. Caulfield, Doug Burger, Derek Chiou | 2019-10-22 |
| 10425472 | Hardware implemented load balancing | Adrian M. Caulfield, Michael Konstantinos Papamichael, Douglas C. Burger, Shlomi Alkalay | 2019-09-24 |
| 10372456 | Tensor processor instruction set architecture | Jeremy Fowers, Kalin Ovtcharov, Steven K. Reinhardt, Ming Liu | 2019-08-06 |
| 10346819 | Mobile device applications, other applications and associated kiosk-based systems and methods for facilitating coin saving | Alexander Stock, Adam Rubin, Theron Sarda, Jonathan Greenblatt, Kevin King +2 more | 2019-07-09 |
| 10338925 | Tensor register files | Jeremy Fowers, Steven K. Reinhardt, Kalin Ovtcharov | 2019-07-02 |
| 10331445 | Multifunction vector processor circuits | Jeremy Fowers, Ming Liu, Kalin Ovtcharov, Steven K. Reinhardt | 2019-06-25 |
| 10326696 | Transmission of messages by acceleration components configured to accelerate a service | Adrian M. Caulfield, Michael Konstantinos Papamichael | 2019-06-18 |
| 10320677 | Flow control and congestion management for acceleration components configured to accelerate a service | Adrian M. Caulfield, Michael Konstantinos Papamichael | 2019-06-11 |
| 10296392 | Implementing a multi-component service using plural hardware acceleration components | Stephen F. Heil, Adrian M. Caulfield, Douglas C. Burger, Andrew R. Putnam | 2019-05-21 |
| 10241970 | Reduced memory nucleotide sequence comparison | Daniel Lo, Kalin Ovtcharov, Ravindra Pandya, David E. Heckerman, Roman Snytsar | 2019-03-26 |
| 10167800 | Hardware node having a matrix vector unit with block-floating point processing | Douglas C. Burger, Daniel Lo, Kalin Ovtcharov | 2019-01-01 |