Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9368546 | Imaging structure with embedded light sources | Rod G. Fleck, David D. Bohn | 2016-06-14 |
| 9270484 | Data center network using circuit switching | Charles P. Thacker, Fang Yu, Thomas L. Rodeheffer | 2016-02-23 |
| 9151984 | Active reflective surfaces | Rod G. Fleck, David D. Bohn | 2015-10-06 |
| 9113033 | Mobile video conferencing with digital annotation | Sasa Junuzovic, Kori Inkpen Quinn, Anoop Gupta, Aaron Hoff, Gina D. Venolia +3 more | 2015-08-18 |
| 8933913 | Electromagnetic 3D stylus | Charles P. Thacker | 2015-01-13 |
| 8901997 | Low noise photo-parametric solid state amplifier | — | 2014-12-02 |
| 8872800 | Optical tablet stylus and indoor navigation system | Charles P. Thacker | 2014-10-28 |
| 8693087 | Passive matrix quantum dot display | Rod G. Fleck | 2014-04-08 |
| 8619065 | Universal stylus device | Charles P. Thacker | 2013-12-31 |
| 8364717 | Hardware accelerated shortest path computation | Daniel Delling, Andrew V. Goldberg, Renato F. Werneck | 2013-01-29 |
| 7559895 | Combining tomographic images in situ with direct vision using a holographic optical element | George DeWitt Stetten | 2009-07-14 |
| 7389389 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Mosur K. Ravishankar | 2008-06-17 |
| 7123211 | Surround-vision display system | — | 2006-10-17 |
| 6988170 | Scalable architecture based on single-chip multiprocessing | Luiz Andre Barroso, Kourosh Gharachorloo | 2006-01-17 |
| 6925537 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets | 2005-08-02 |
| 6912624 | Method and system for exclusive two-level caching in a chip-multiprocessor | Luiz Andre Barroso, Kourosh Gharachorloo | 2005-06-28 |
| 6751720 | Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy | Luiz Andre Barroso, Kourosh Gharachorloo, Robert Stets, Mosur K. Ravishankar | 2004-06-15 |
| 6725343 | System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system | Luiz Andre Barroso, Kourosh Gharachorloo | 2004-04-20 |
| 6725334 | Method and system for exclusive two-level caching in a chip-multiprocessor | Luiz Andre Barroso, Kourosh Gharachorloo | 2004-04-20 |
| 6697919 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Mosur K. Ravishankar | 2004-02-24 |
| 6675265 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets | 2004-01-06 |
| 6668308 | Scalable architecture based on single-chip multiprocessing | Luiz Andre Barroso, Kourosh Gharachorloo | 2003-12-23 |
| 6636949 | System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing | Luiz Andre Barroso, Kourosh Gharachorloo, Robert Stets, Mosur K. Ravishankar | 2003-10-21 |
| 6622217 | Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets | 2003-09-16 |
| 6262823 | System for optical time domain multiplexing of digital signals | — | 2001-07-17 |