Issued Patents All Time
Showing 101–125 of 178 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6166942 | Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines | Huy T. Vo, Layne Bunker | 2000-12-26 |
| 6163860 | Layout for a semiconductor memory device having redundant elements | — | 2000-12-19 |
| 6154864 | Read only memory embedded in a dynamic random access memory | — | 2000-11-28 |
| 6144575 | Die architecture accommodating high-speed semiconductor devices | Donald M. Morgan | 2000-11-07 |
| 6141286 | Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines | Huy T. Vo, Layne Bunker | 2000-10-31 |
| 6121822 | Charge pump circuit for generating a substrated bias | — | 2000-09-19 |
| 6118711 | Apparatus for testing redundant elements in a packaged semiconductor memory device | — | 2000-09-12 |
| 6104643 | Integrated circuit clock input buffer | — | 2000-08-15 |
| 6072728 | Data output buffer | — | 2000-06-06 |
| 6055208 | Method and circuit for sending a signal in a semiconductor device during a setup time | Donald M. Morgan | 2000-04-25 |
| 6055172 | Single deposition layer metal dynamic random access memory | — | 2000-04-25 |
| 6055202 | Multi-bank architecture for a wide I/O DRAM | — | 2000-04-25 |
| 6052325 | Method and apparatus for translating signals | — | 2000-04-18 |
| 6049489 | Methods using a data read latch circuit in a semiconductor device | — | 2000-04-11 |
| 6043107 | Method for producing an integrated circuit assembly | — | 2000-03-28 |
| 6018811 | Layout for semiconductor memory device wherein intercoupling lines are shared by two sets of fuse banks and two sets of redundant elements not simultaneously active | — | 2000-01-25 |
| 6011727 | Block write circuit and method for wide data path memory devices | Layne Bunker | 2000-01-04 |
| 5995402 | Die architecture accommodating high-speed semiconductor devices | Donald M. Morgan | 1999-11-30 |
| 5991214 | Circuit and method for varying a period of an internal control signal during a test mode | Paul S. Zagar | 1999-11-23 |
| 5986944 | Method and apparatus using a data read latch circuit in a semiconductor device | — | 1999-11-16 |
| 5986916 | On-chip program voltage generator for antifuse repair | Kevin G. Duesman | 1999-11-16 |
| 5986488 | Method and apparatus for fast reset of a one-shot circuit | — | 1999-11-16 |
| 5983314 | Output buffer having inherently precise data masking | — | 1999-11-09 |
| 5978302 | Multi-bank architecture for a wide I/O DRAM | — | 1999-11-02 |
| 5978289 | Apparatus for testing redundant elements in a packaged semiconductor memory device | — | 1999-11-02 |