Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8450175 | Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith | Jaydip Guha, Shyam Surthi, Kamal M. Karda, Hung-Ming Tsai | 2013-05-28 |
| 8378430 | Transistors having argon gate implants and methods of forming the same | Cancheepuram V. Srividya, Dan Gealy | 2013-02-19 |
| 8158471 | Capacitorless DRAM on bulk silicon | Jigish Trivedi | 2012-04-17 |
| 8067286 | Methods of forming recessed access devices associated with semiconductor constructions | Kunal R. Parekh, Jigish Trivedi, John K. Zahurak, Sanh D. Tang | 2011-11-29 |
| 7897460 | Methods of forming recessed access devices associated with semiconductor constructions | Kunal R. Parekh, Jigish Trivedi, John K. Zahurak, Sanh D. Tang | 2011-03-01 |
| 7858458 | CMOS fabrication | — | 2010-12-28 |
| 7829399 | Capacitorless DRAM on bulk silicon | Jigish Trivedi | 2010-11-09 |
| 7601591 | Method of manufacturing sidewall spacers on a memory device, and device comprising same | David K. Hwang, Kunal R. Parekh, Michael Willett, Jigish Trivedi, Greg Peterson | 2009-10-13 |
| 7538389 | Capacitorless DRAM on bulk silicon | Jigish Trivedi | 2009-05-26 |
| 7517744 | Capacitorless DRAM on bulk silicon | Jigish Trivedi | 2009-04-14 |
| 7462534 | Methods of forming memory circuitry | Kunal R. Parekh, Steve V. Cole | 2008-12-09 |
| 7459742 | Method of manufacturing sidewall spacers on a memory device, and device comprising same | David K. Hwang, Kunal R. Parekh, Michael Willett, Jigish Trivedi, Greg Peterson | 2008-12-02 |
| 7384849 | Methods of forming recessed access devices associated with semiconductor constructions | Kunal R. Parekh, Jigish Trivedi, John K. Zahurak, Sanh D. Tang | 2008-06-10 |
| 7341906 | Method of manufacturing sidewall spacers on a memory device, and device comprising same | David K. Hwang, Kunal R. Parekh, Michael Willett, Jigish Trivedi, Greg Peterson | 2008-03-11 |
| 7332388 | Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same | Jigish Trivedi | 2008-02-19 |
| 7005342 | Method to fabricate surface p-channel CMOS | Jigish Trivedi | 2006-02-28 |
| 6809014 | Method to fabricate surface p-channel CMOS | Jigish Trivedi | 2004-10-26 |
| 6797596 | Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device | Fawad Ahmed, Jigish Trivedi | 2004-09-28 |