Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5864499 | Non-volatile data storage unit and method of controlling same | Frankie F. Roohparvar | 1999-01-26 |
| 5862077 | Fast sensing amplifier for flash memory | — | 1999-01-19 |
| 5835411 | Computer including a fast sensing amplifier | — | 1998-11-10 |
| 5801985 | Memory system having programmable control parameters | Frankie F. Roohparvar, Darrell Rinerson, Christophe J. Chevallier | 1998-09-01 |
| 5767711 | Level detection circuit and method | Christophe J. Chevallier, Frankie F. Roohparvar | 1998-06-16 |
| 5757697 | Method for sensing the binary state of a floating-gate memory device | — | 1998-05-26 |
| 5721702 | Reference voltage generator using flash memory cells | — | 1998-02-24 |
| 5706235 | Memory circuit with switch for selectively connecting an I/O pad directly to a nonvolatile memory cell and method for operating same | Fariborz F. Roohparvar | 1998-01-06 |
| 5694366 | OP amp circuit with variable resistance and memory system including same | Christophe J. Chevallier | 1997-12-02 |
| 5682345 | Non-volatile data storage unit method of controlling same | Frankie F. Roohparvar | 1997-10-28 |
| 5677879 | Method and apparatus for performing memory cell verification on a nonvolatile memory circuit | Fariborz F. Roohparvar | 1997-10-14 |
| 5631864 | Memory array having a reduced number of metal source lines | — | 1997-05-20 |
| 5619150 | Switch for minimizing transistor exposure to high voltage | — | 1997-04-08 |
| 5594694 | Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell | Fariborz F. Roohparvar | 1997-01-14 |
| 5581206 | Power level detection circuit | Christophe J. Chevallier, Frankie F. Roohparvar | 1996-12-03 |
| 5579274 | Sense circuit for a flash eefprom cell having a negative delta threshold voltage | Michael A. Van Buskirk | 1996-11-26 |
| 5568426 | Method and apparatus for performing memory cell verification on a nonvolatile memory circuit | Fariborz F. Roohparvar | 1996-10-22 |
| 5559990 | Memories with burst mode access | Pearl Po-Yee Cheng, James Yu | 1996-09-24 |
| 5477499 | Memory architecture for a three volt flash EEPROM | Michael A. Van Buskirk | 1995-12-19 |
| 5231602 | Apparatus and method for improving the endurance of floating gate devices | Nader Radjy | 1993-07-27 |
| 5101378 | Optimized electrically erasable cell for minimum read disturb and associated method of sensing | Nader Radjy | 1992-03-31 |
| 5005155 | Optimized electrically erasable PLA cell for minimum read disturb | Nader Radjy | 1991-04-02 |
| 4935648 | Optimized E.sup.2 pal cell for minimum read disturb | Nader Radjy | 1990-06-19 |
| 4714901 | Temperature compensated complementary metal-insulator-semiconductor oscillator | Babu Jain, Pardeep K. Jain | 1987-12-22 |
| 4629972 | Temperature insensitive reference voltage circuit | Paul I. Suciu | 1986-12-16 |