Issued Patents All Time
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8351285 | Systems, memories, and methods for repair in open digit memory architectures | Michael S. Lane | 2013-01-08 |
| 8009460 | Device and method for using dynamic cell plate sensing in a DRAM memory cell | Brian Callaway | 2011-08-30 |
| 7684228 | Device and method for using dynamic cell plate sensing in a DRAM memory cell | Brian Callaway | 2010-03-23 |
| 7593272 | Detection of row-to-row shorts and other row decode defects in memory devices | Daniel Doyle | 2009-09-22 |
| 7558102 | Device and method having a memory array storing each bit in multiple memory cells | — | 2009-07-07 |
| 7307896 | Detection of row-to-row shorts and other row decode defects in memory devices | Daniel Doyle | 2007-12-11 |
| 7251155 | Device and method having a memory array storing each bit in multiple memory cells | — | 2007-07-31 |
| 7251173 | Combination column redundancy system for a memory array | Aron T. Lunde | 2007-07-31 |
| 7164595 | Device and method for using dynamic cell plate sensing in a DRAM memory cell | Brian Callaway | 2007-01-16 |
| 6958945 | Device having a memory array storing each bit in multiple memory cells | — | 2005-10-25 |
| 6947346 | Reducing digit equilibrate current during self-refresh mode | Brian Callaway | 2005-09-20 |
| 6925021 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Timoty B. Cowles, Patrick J. Mullarkey | 2005-08-02 |
| 6853601 | Device and method for repairing a memory array by storing each bit in multiple memory cells in the array | — | 2005-02-08 |
| 6850457 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMS | Timoty B. Cowles, Patrick J. Mullarkey | 2005-02-01 |
| 6839300 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Timoty B. Cowles, Patrick J. Mullarkey | 2005-01-04 |
| 6781901 | Sacrifice read test mode | — | 2004-08-24 |
| 6711093 | Reducing digit equilibrate current during self-refresh mode | Brian Callaway | 2004-03-23 |
| 6701470 | Method for testing a memory device having different number of data pads than the tester | Patrick J. Mullarkey | 2004-03-02 |
| 6691247 | Circuit and method for masking a dormant memory cell | — | 2004-02-10 |
| 6556497 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Timothy B. Cowles, Patrick J. Mullarkey | 2003-04-29 |
| 6552940 | Sacrifice read test mode | — | 2003-04-22 |
| 6538949 | Device and method for repairing a memory array by storing each bit in multiple memory cells in the array | — | 2003-03-25 |
| 6519201 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Timoty B. Cowles, Patrick J. Mullarkey | 2003-02-11 |
| 6459635 | Apparatus and method for increasing test flexibility of a memory device | Patrick J. Mullarkey | 2002-10-01 |
| 6449203 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Timoty B. Cowles, Patrick J. Mullarkey | 2002-09-10 |