Issued Patents All Time
Showing 326–350 of 522 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6901008 | Flash memory with RDRAM interface | Kevin C. Widmer | 2005-05-31 |
| 6891758 | Position based erase verification levels in a flash memory device | — | 2005-05-10 |
| 6892270 | Synchronous flash memory emulating the pin configuration of SDRAM | — | 2005-05-10 |
| 6886071 | Status register to improve initialization of a synchronous memory | — | 2005-04-26 |
| 6883044 | Synchronous flash memory with simultaneous access to one or more banks | — | 2005-04-19 |
| 6876583 | Non-volatile memory erase circuitry | — | 2005-04-05 |
| 6877100 | Adjustable timing circuit of an integrated circuit by selecting and moving clock edges based on a signal propagation time stored in a programmable non-volatile fuse circuit | Dean Nobunaga | 2005-04-05 |
| 6877080 | Flash with consistent latency for read operations | — | 2005-04-05 |
| 6873507 | Electrostatic discharge protection with input impedance | — | 2005-03-29 |
| 6873564 | Zero latency-zero bus turnaround synchronous flash memory | — | 2005-03-29 |
| 6870770 | Method and architecture to calibrate read operations in synchronous flash memory | — | 2005-03-22 |
| 6870774 | Flash memory architecture for optimizing performance of memory having multi-level memory cells | Kevin C. Widmer, Cliff Zitlaw | 2005-03-22 |
| 6865111 | Method and architecture to calibrate read operations in synchronous flash memory | — | 2005-03-08 |
| 6865702 | Synchronous flash memory with test code input | — | 2005-03-08 |
| 6862222 | Non-volatile memory device with erase address register | — | 2005-03-01 |
| 6859392 | Preconditioning global bitlines | Ebrahim Abedifard | 2005-02-22 |
| 6851026 | Synchronous flash memory with concurrent write and read operation | — | 2005-02-01 |
| 6847565 | Memory with row redundancy | Ebrahim Abedifard | 2005-01-25 |
| 6845057 | DDR synchronous flash memory with virtual segment architecture | Kevin C. Widmer, Cliff Zitlaw | 2005-01-18 |
| 6842385 | Automatic reference voltage regulation in a memory device | Dumitru Cioaca, Christophe J. Chevallier, Al Vahidimowlavi | 2005-01-11 |
| 6839875 | Method and apparatus for performing error correction on data read from a multistate memory | — | 2005-01-04 |
| 6836434 | Mode selection in a flash memory device | — | 2004-12-28 |
| 6819622 | Write and erase protection in a synchronous memory | Ebrahim Abedifard | 2004-11-16 |
| 6810512 | Integrated circuit with layout matched high speed lines | — | 2004-10-26 |
| 6809960 | High speed low voltage driver | Ebrahim Abedifard | 2004-10-26 |