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High speed serial peripheral interface memory subsystem |
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Top/bottom symmetrical protection scheme for flash |
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Top/bottom symmetrical protection scheme for flash |
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2007-02-13 |
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Flash memory architecture for optimizing performance of memory having multi-level memory cells |
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Frankie F. Roohparvar |
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2005-06-14 |
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2005-05-31 |
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Flash memory architecture for optimizing performance of memory having multi-level memory cells |
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DDR synchronous flash memory with virtual segment architecture |
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2005-01-18 |
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Synchronous flash memory with virtual segment architecture |
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2004-05-25 |
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Frankie F. Roohparvar |
2004-04-20 |
| 6667932 |
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2003-12-23 |
| 6654307 |
DDR synchronous flash memory with virtual segment architecture |
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2003-11-25 |
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Top/bottom symmetrical protection scheme for flash |
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2003-11-25 |
| 6625081 |
Synchronous flash memory with virtual segment architecture |
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2003-09-23 |
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Erase block architecture for non-volatile memory |
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2003-07-01 |
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Flash memory with DDRAM interface |
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2003-05-27 |
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Non-volatile memory with address descrambling |
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2003-04-15 |
