Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11488685 | Adjustable column address scramble using fuses | James S. Rehmeyer, George B. Raad, Seth A. Eichmeyer, Dean D. Gans | 2022-11-01 |
| 11450388 | Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems | James S. Rehmeyer | 2022-09-20 |
| 11437116 | System and method for counting fail bit and reading out the same | Christian Mohr, Gregg D. Wolff, C. Omar Benitez, Dennis G. Montierth | 2022-09-06 |
| 11263078 | Apparatuses, systems, and methods for error correction | Yoshinori Fujiwara, Vivek Kotti, Jason Johnson, Kevin G. Werhane | 2022-03-01 |
| 11244741 | Selectable fuse sets, and related methods, devices, and systems | James S. Rehmeyer, Seth A. Eichmeyer | 2022-02-08 |
| 11232849 | Memory device with a repair match mechanism and methods for operating the same | — | 2022-01-25 |
| 11217296 | Staggered refresh counters for a memory device | James S. Rehmeyer | 2022-01-04 |
| 11212142 | Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device | Jason Johnson | 2021-12-28 |
| 11138107 | Modifying subsets of memory bank operating parameters | Alan J. Wilson | 2021-10-05 |
| 11139045 | Memory device with a memory repair mechanism and methods for operating the same | James S. Rehmeyer, Seth A. Eichmeyer | 2021-10-05 |
| 11120860 | Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems | James S. Rehmeyer | 2021-09-14 |
| 11114181 | Memory devices with redundant memory cells for replacing defective memory cells, and related systems and methods | James S. Rehmeyer, Seth A. Eichmeyer, Kenji Yoshida | 2021-09-07 |
| 11069426 | Memory device with a row repair mechanism and methods for operating the same | James S. Rehmeyer, Seth A. Eichmeyer | 2021-07-20 |
| 11017879 | Adjustable column address scramble using fuses | James S. Rehmeyer, George B. Raad, Seth A. Eichmeyer, Dean D. Gans | 2021-05-25 |
| 11011250 | Modifying memory bank operating parameters | Alan J. Wilson | 2021-05-18 |
| 10984884 | Configurable associated repair addresses and circuitry for a memory device | Kevin G. Werhane | 2021-04-20 |
| 10937517 | Apparatuses and methods to encode column plane compression data | Eric J. Rich-Plotkin, Boon Hor Lam, Greg S. Hendrix, Shawn M. Hilde, Jiyun Li +1 more | 2021-03-02 |
| 10923172 | Apparatuses and methods for multi-bank refresh timing | Jason Johnson, Daniel S. Miller, Yoshinori Fujiwara | 2021-02-16 |
| 10855495 | Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device | Jason Johnson | 2020-12-01 |
| 10825544 | Configurable post-package repair | Kevin G. Werhane | 2020-11-03 |
| 10643734 | System and method for counting fail bit and reading out the same | Christian Mohr, Gregg D. Wolff, C. Omar Benitez, Dennis G. Montierth | 2020-05-05 |
| 10600496 | Modifying memory bank operating parameters | Alan J. Wilson | 2020-03-24 |
| 10593392 | Apparatuses and methods for multi-bank refresh timing | Jason Johnson, Daniel S. Miller, Yoshinori Fujiwara | 2020-03-17 |
| 10530613 | Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device | Jason Johnson | 2020-01-07 |
| 10193711 | Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device | Jason Johnson | 2019-01-29 |