| 12387780 |
Testing memory of wafer-on-wafer bonded memory and logic |
Kunal R. Parekh, Glen E. Hush, Sean S. Eilert |
2025-08-12 |
| 12354649 |
Signal routing between memory die and logic die for performing operations |
Sean S. Eilert, Glen E. Hush, Kunal R. Parekh |
2025-07-08 |
| 12165696 |
Signal routing between memory die and logic die |
Sean S. Eilert, Glen E. Hush, Kunal R. Parekh |
2024-12-10 |
| 12118460 |
Discovery of hardware characteristics of deep learning accelerators for optimization via compiler |
Marko Vitez, Eugenio Culurciello, Jaime Cummins, Andre Xian Ming Chang |
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| 12112792 |
Memory device for wafer-on-wafer formed memory and logic |
Glen E. Hush, Sean S. Eilert, Kunal R. Parekh |
2024-10-08 |
| 12112793 |
Signal routing between memory die and logic die for mode based operations |
Glen E. Hush, Sean S. Eilert, Kunal R. Parekh |
2024-10-08 |
| 12094531 |
Caching techniques for deep learning accelerator |
Patrick Estep, David A. Roberts |
2024-09-17 |
| 12007899 |
Delta predictions for page scheduling |
David A. Roberts, Patrick Michael Sheridan, Lukasz Burzawa |
2024-06-11 |
| 11915742 |
Wafer-on-wafer formed memory and logic for genomic annotations |
Sean S. Eilert, Kunal R. Parekh, Glen E. Hush |
2024-02-27 |
| 11861337 |
Deep neural networks compiler for a trace-based accelerator |
Andre Xian Ming Chang, Eugenio Culurciello, Marko Vitez |
2024-01-02 |
| 11829627 |
Data migration schedule prediction using machine learning |
David A. Roberts |
2023-11-28 |
| 11775313 |
Hardware accelerator for convolutional neural networks and method of operation thereof |
Eugenio Culurciello, Vinayak Anand Gokhale, Andre Xian Ming Chang |
2023-10-03 |
| 11675624 |
Inference engine circuit architecture |
Andre Xian Ming Chang, Eugenio Culurciello |
2023-06-13 |