Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6345353 | Stack pointer with post increment/decrement allowing selection from parallel read/write address outputs | Stephen M. Allen | 2002-02-05 |
| 6321319 | Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction | Rodney Drake, Randy Yach, Joseph W. Triece, Jennifer Chiao, Steve Allen | 2001-11-20 |
| 6243798 | Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction | Rodney Drake, Randy Yach, Joseph W. Triece, Jennifer Chiao, Steve Allen | 2001-06-05 |
| 6230275 | Circuit for powering down unused configuration bits to minimize power consumption | Joseph W. Triece, Rodney Drake | 2001-05-08 |
| 6225678 | Layout technique for a matching capacitor array using a continuous top electrode | Randy Yach | 2001-05-01 |
| 6205539 | Method for manipulating a stack pointer with post increment/decrement operation | Stephen M. Allen | 2001-03-20 |
| 6098160 | Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor | Rodney Drake, Randy Yach, Joseph W. Triece, Brian Boles, Darrel Johansen | 2000-08-01 |
| 6057705 | Programmable pin designation for semiconductor devices | Rodney Drake, Brian Boles | 2000-05-02 |
| 6029241 | Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor | Sumit Mitra, Rodney Drake | 2000-02-22 |
| 6016019 | Capacitor array arrangement for improving capacitor array matching | — | 2000-01-18 |
| 5958039 | Master-slave latches and post increment/decrement operations | Stephen M. Allen | 1999-09-28 |
| 5874863 | Phase locked loop with fast start-up circuitry | Jennifer Chiao | 1999-02-23 |
| 5178284 | Compact disc stand | — | 1993-01-12 |