Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11113441 | Reduce/broadcast computation-enabled switching elements in an emulation network | Jean-Marc Brault, Jean-Paul Clavequin, Laurent Vuillemin | 2021-09-07 |
| 10664563 | Concurrent testbench and software driven verification | Debdutta Bhattacharya, Ayub Akbar Khan | 2020-05-26 |
| 10664566 | Bandwidth test in networking System-on-Chip verification | Suresh Krishnamurthy, Deepak Garg, Saurabh Khaitan, Sanjay Gupta, John R. Stickley +2 more | 2020-05-26 |
| 10657217 | Latency test in networking system-on-chip verification | Suresh Krishnamurthy, Deepak Garg, Sudhanshu Jayaswal, Saurabh Khaitan, Sanjay Gupta +4 more | 2020-05-19 |
| 10579776 | Selective conditional stall for hardware-based circuit design verification | Ansuman Prusty, Vipul Kulshrestha, Kenneth W. Crouch, Matthew L. Dahl, Laurent Vuillemin | 2020-03-03 |
| 10503848 | Target capture and replay in emulation | Krishnamurthy Suresh, Satish Kumar Agarwal, Sanjay Gupta | 2019-12-10 |
| 10410713 | Content addressable memory modeling in emulation and prototyping | Sanjay Gupta, Krishnamurthy Suresh, Praveen Shukla, Saurabh Gupta | 2019-09-10 |
| 9898563 | Modeling memory in emulation based on cache | Krishnamurthy Suresh, Mukesh Gupta, Sanjay Gupta | 2018-02-20 |
| 9767237 | Target capture and replay in emulation | Krishnamurthy Suresh, Satish Kumar Agarwal, Sanjay Gupta | 2017-09-19 |
| 9703579 | Debug environment for a multi user hardware assisted verification system | Krishnamurthy Suresh, Sanjay Gupta, Amit Jain | 2017-07-11 |
| 9619600 | Third party component debugging for integrated circuit design | Krishnamurthy Suresh, Sanjay Gupta | 2017-04-11 |
| 9305126 | Switching activity reduction through retiming | Sanjay Gupta, Praveen Shukla, Saurabh Gupta, Jeffrey W. Evans | 2016-04-05 |
| 9165099 | Adaptive clock management in emulation | Krishnamurthy Suresh, Sanjay Gupta, Amit Jain, Satish Kumar Agarwal | 2015-10-20 |
| 8868974 | Memory-based trigger generation scheme in an emulation environment | Gregoire Brunot | 2014-10-21 |
| 8843861 | Third party component debugging for integrated circuit design | — | 2014-09-23 |
| 8516411 | Register transfer level design compilation advisor | Sanjay Gupta, Praveen Shukla | 2013-08-20 |
| 8352242 | Communication scheme between programmable sub-cores in an emulation environment | Peer Schmitt, Philippe Diehl | 2013-01-08 |
| 8181129 | Acyclic modeling of combinational loops | Amit Gupta | 2012-05-15 |
| 8108198 | Memory tracing in an emulation environment | Peer Schmitt, Philippe Diehl, Cyril Quennesson | 2012-01-31 |
| 8108729 | Memory-based trigger generation scheme in an emulation environment | Gregoire Brunot | 2012-01-31 |
| 7964000 | Biodiesel fuel blend | — | 2011-06-21 |
| 7730353 | Memory-based trigger generation scheme in an emulation environment | Gregoire Brunot | 2010-06-01 |
| 7480610 | Software state replay | David Scott, Joshua Marantz, Frederic Reblewski | 2009-01-20 |
| 7458998 | Blending biodiesel with diesel fuel in cold locations | Ken Copeland, Rita Hardy, Jeff Johnson, Kirk Walztoni | 2008-12-02 |
| 7454722 | Acyclic modeling of combinational loops | Amit Gupta | 2008-11-18 |