Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8664071 | Castellated gate MOSFET tetrode capable of fully-depleted operation | — | 2014-03-04 |
| 8138544 | Castellated gate MOSFET tetrode capable of fully-depleted operation | — | 2012-03-20 |
| 7968409 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof | — | 2011-06-28 |
| 7719058 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof | — | 2010-05-18 |
| 7714384 | Castellated gate MOSFET device capable of fully-depleted operation | — | 2010-05-11 |
| 7439139 | Fully-depleted castellated gate MOSFET device and method of manufacture thereof | — | 2008-10-21 |
| 7211864 | Fully-depleted castellated gate MOSFET device and method of manufacture thereof | — | 2007-05-01 |
| 6525377 | Low threshold voltage MOS transistor and method of manufacture | — | 2003-02-25 |
| 6355532 | Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET | Verne Hornback, David W. Daniel | 2002-03-12 |
| 6316817 | MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor | David W. Daniel, Todd A. Randazzo | 2001-11-13 |
| 6284586 | Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking | Derryl D. J. Allman, John Gregory, James P. Yakura, Dim-Lee Kwong | 2001-09-04 |
| 6115233 | Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region | Derryl D. J. Allman, John Gregory, James P. Yakura, Dim-Lee Kwong | 2000-09-05 |
| 5985705 | Low threshold voltage MOS transistor and method of manufacture | — | 1999-11-16 |
| 5858828 | Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor | David W. Daniel, Todd A. Randazzo | 1999-01-12 |
| 5780329 | Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask | Todd A. Randazzo | 1998-07-14 |