Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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James Steele — 12 Patents

VTVlsi Technology: 5 patents #103 of 594Top 20%
Philips: 3 patents #1,693 of 7,731Top 25%
DLDialog Semiconductor (Uk) Limited: 2 patents #107 of 310Top 35%
PSPhilips Semiconductors: 1 patents #15 of 64Top 25%
RLRenesas Design (Uk) Limited: 1 patents #4 of 22Top 20%
Chandler, AZ: #494 of 3,331 inventorsTop 15%
Arizona: #3,054 of 32,909 inventorsTop 10%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
James Steele has been granted 12 US patents while listed as an inventor at Vlsi Technology. The first was granted in 1997 and the most recent in January 2025. James Steele ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list James Steele in Chandler, AZ, US.

Patents per Year

Patents granted per year, 1997 to 2025Bar chart with a peak of 4 patents in 1998.peak 41997: 1 patents19971998: 4 patents19982001: 2 patents20012002: 1 patents20022004: 1 patents20042021: 1 patents20212022: 1 patents20222025: 1 patents2025

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12199503 Driver for switched mode power supply John William Kesterson 2025-01-14
11539294 Multi-level power converter with light load flying capacitor voltage regulation Aravind Mangudi, Mark Mercer, Taek Chang, Bill McKillop 2022-12-27
10998818 Asynchronous dropout transition for multi-level and single-level buck converters John William Kesterson, Aravind Mangudi, Mark Mercer 2021-05-04
6782466 Arrangement and method for accessing data in a virtual memory arrangement Desi Rhoden, George Crouse 2004-08-24 $759,000
6385749 Method and arrangement for controlling multiple test access port control modules Swaroop Adusumilli, David K. Cassetti 2002-05-07 $9,301,000
6334198 Method and arrangement for controlling multiply-activated test access port control modules Swaroop Adusumilli, David K. Cassetti 2001-12-25
6311302 Method and arrangement for hierarchical control of multiple test access port control modules David K. Cassetti, Swaroop Adusumilli 2001-10-30
5815675 Method and apparatus for direct access to main memory by an I/O bus Barry Davis, Philip Wszolek, Brian Fall, Swaroop Adusumilli, David K. Cassetti +2 more 1998-09-29 $1,078,000
5799178 System and method for starting and maintaining a central processing unit (CPU) clock using clock division emulation (CDE) during break events Gary Walker, Mike Crews 1998-08-25 $4,482,000
5793992 Method and apparatus for arbitrating access to main memory of a computer system Barry Davis, Philip Wszolek, Brian Fall, Swaroop Adusumilli, David K. Cassetti +2 more 1998-08-11 $1,556,000
5732226 Apparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI bus Philip Wszolek, Rodney J. Pesavento, Brian Fall 1998-03-24 $3,276,000
5664213 Input/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus Gary D. Hicok, David R. Evoy, Gary Walker, Joseph A. Thomsen, Lonnie C. Goff 1997-09-02 $25,946,000