ZC

Zhong-Ning Cai

IN Intel: 22 patents #1,785 of 30,777Top 6%
AM AMD: 4 patents #2,565 of 9,279Top 30%
Overall (All Time): #172,766 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11164806 Temperature calculation based on non-uniform leakage power Dhananjay Adhikari, Jacob Schneider 2021-11-02
10542268 System for video compression Haibin Li, Zhen Chen, Lei Zhang, Ji Zhou 2020-01-21
10368087 Dynamic reload of video encoder motion estimation search window under performance/power constraints Ihab Amer, Gabor Sines, Edward A. Harold, Jinbo Qiu, Lei Zhang +4 more 2019-07-30
10078592 Resolving multi-core shared cache access conflicts Krishnakanth V. Sistla, Yen-Cheng Liu, Jeffrey D. Gilbert 2018-09-18
10031848 Method and apparatus for improving snooping performance in a multi-core multi-processor Krishnakanth V. Sistla, Yen-Cheng Liu 2018-07-24
9507534 Home agent multi-level NVM memory architecture Dimitrios Ziakas 2016-11-29
9361257 Mechanism for facilitating customization of multipurpose interconnect agents at computing devices Dimitrios Ziakas 2016-06-07
9256277 Method and apparatus for thermal sensitivity based dynamic power control of a processor 2016-02-09
9208110 Raw memory transaction support Robert J. Safranek, Robert G. Blankenship 2015-12-08
8966301 Method and apparatus for thermal sensitivity based dynamic power control of a processor 2015-02-24
8788859 Thermal sensitivity based clock frequency adjustment for dynamic power control of a processor 2014-07-22
8407432 Cache coherency sequencing implementation and adaptive LLC access priority control for CMP Krishnakanth V. Sistla, Yen-Cheng Liu, Jeffrey D. Gilbert 2013-03-26
7991963 In-memory, in-page directory cache coherency scheme Ian M. Steiner, Saurabh Tiwari, Kai Cheng 2011-08-02
7822998 Method and apparatus for thermal sensitivity based dynamic power control 2010-10-26
7360008 Enforcing global ordering through a caching bridge in a multicore multiprocessor system Krishnakanth V. Sistla, Yen-Cheng Liu 2008-04-15
7228387 Apparatus and method for an adaptive multiple line prefetcher William G. Auld, Jeffrey D. Gilbert 2007-06-05
7100060 Techniques for utilization of asymmetric secondary processing resources Chee How Lim 2006-08-29
7028144 Method and apparatus for an in-situ victim cache William G. Auld 2006-04-11
6718475 Multi-processor mobile computer system having one processor integrated with a chipset 2004-04-06
6631474 System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching Tosaku Nakanishi 2003-10-07
6583648 Method and apparatus for fine granularity clock gating 2003-06-24
6501999 Multi-processor mobile computer system having one processor integrated with a chipset 2002-12-31
6470422 Buffer memory management in a system having multiple execution entities Tosaku Nakanishi 2002-10-22
6349363 Multi-section cache with different attributes for each section Tosaku Nakanishi 2002-02-19