Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11322194 | Compensating offsets in buffers and related systems, methods, and devices | Minoru Someya, Sadayuki Okuma | 2022-05-03 |
| 10937486 | Compensating offsets in buffers and related systems, methods, and devices | Minoru Someya, Sadayuki Okuma | 2021-03-02 |
| 7710142 | Semiconductor integrated circuit | Ryo HIRANO, Hidekazu Egawa | 2010-05-04 |
| 7216198 | DRAM with super self-refresh and error correction for extended period between refresh operations | Yutaka Ito, Takayuki Aisu | 2007-05-08 |
| 6707139 | Semiconductor device with plural unit regions in which one or more MOSFETs are formed | Isamu Fujii, Kiyoshi Nakai, Sadayuki Morita, Hidekazu Egawa, Katura Abe +1 more | 2004-03-16 |
| 6633508 | Semiconductor memory device and memory system | Masaya Muranaka, Shinichi Miyatake, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame | 2003-10-14 |
| 6518835 | Semiconductor integrated circuit device having an optimal circuit layout to ensure stabilization of internal source voltages without lowering circuit functions and/or operating performance | Yoshiro Riho, Kiyoshi Nakai, Hidekazu Egawa, Isamu Fujii | 2003-02-11 |
| 6411160 | Semiconductor integrated circuit device | Yoshiro Riho, Kiyoshi Nakai, Hidekazu Egawa, Isamu Fujii | 2002-06-25 |
| 6282141 | Semiconductor memory device and memory system | Masaya Muranaka, Shinichi Miyatake, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame | 2001-08-28 |
| 6274895 | Semiconductor integrated circuit device | Isamu Fujii, Kiyoshi Nakai, Sadayuki Morita, Hidekazu Egawa, Katura Abe +1 more | 2001-08-14 |
| 6064605 | Semiconductor memory device and memory system | Masaya Muranaka, Shinichi Miyatake, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame | 2000-05-16 |
| 5969996 | Semiconductor memory device and memory system | Masaya Muranaka, Shinichi Miyatake, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame | 1999-10-19 |
| 5862086 | Semiconductor storage device | Chisa Makimura, Shunichi Sukegawa, Hiroyuki Fujiwara, Masayuki Hira | 1999-01-19 |
| 5844915 | Method for testing word line leakage in a semiconductor memory device | Yoritaka Saitoh, Shunichi Sukegawa, Makoto Saeki | 1998-12-01 |
| 5831910 | Semiconductor integrated circuit utilizing overdriven differential amplifiers | Noriaki Kubota, Kouji Arai, Tsugio Takahashi, Shunichi Sukegawa, Koichi Abe | 1998-11-03 |
| 5818784 | Semiconductor memory device and memory system | Masaya Muranaka, Shinichi Miyatake, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame | 1998-10-06 |
| 5805522 | Address access path control circuit | Shunichi Sukegawa, Koichi Abe, Makoto Saeki | 1998-09-08 |
| 5768214 | Semiconductor memory device | Ken Saitoh, Shunichi Sukegawa, Tadashi Tachibana, Makoto Saeki | 1998-06-16 |
| 5764580 | Semiconductor integrated circuit | Tsugio Takahashi, Shunichi Sukegawa, Koichi Abe | 1998-06-09 |
| 5761149 | Dynamic RAM | Kanehide Kenmizaki, Tsugio Takahashi, Masayuki Nakamura, Makoto Saeki, Chisa Makimura +2 more | 1998-06-02 |
| 5625234 | Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium | Hiroyuki Yoshida | 1997-04-29 |
| 5615156 | Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines | Hiroyuki Yoshida, Takashi Inui, Shigeki Numaga, Kiyoshi Nakai | 1997-03-25 |
| 5598373 | Semiconductor memory system | Shoji Wada, Kanehide Kenmizaki, Masaya Muranaka, Masahiro Ogata, Hidetomo Aoyagi +8 more | 1997-01-28 |
| 5557580 | Word line driving circuit | Shigeki Numaga, Shunichi Sukegawa, Takashi Inui, Kiyoshi Nakai | 1996-09-17 |
| 5497349 | Dynamic random access memory device having first and second I/O line groups isolated from each other | Kiyoshi Nakai, Takashi Inui | 1996-03-05 |