Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11810634 | Computer system with redundancy having fail test mode | — | 2023-11-07 |
| 11610623 | Apparatus with a row-hammer address latch mechanism | — | 2023-03-21 |
| 11322194 | Compensating offsets in buffers and related systems, methods, and devices | Minoru Someya, Yukihide Suzuki | 2022-05-03 |
| 10943637 | Apparatus with a row-hammer address latch mechanism | — | 2021-03-09 |
| 10937486 | Compensating offsets in buffers and related systems, methods, and devices | Minoru Someya, Yukihide Suzuki | 2021-03-02 |
| 10153016 | Apparatus of offset voltage adjustment in input buffer | — | 2018-12-11 |
| 9792964 | Apparatus of offset voltage adjustment in input buffer | — | 2017-10-17 |
| 8987735 | Semiconductor device | Takahiro Koyama | 2015-03-24 |
| 8958258 | Semiconductor device and test method thereof | — | 2015-02-17 |
| 8648339 | Semiconductor device including first semiconductor chip including first pads connected to first terminals, and second semiconductor chip including second pads connected to second terminals | Takahiro Koyama | 2014-02-11 |
| 7826295 | Semiconductor memory device including a repair circuit which includes mode fuses | Atsushi Masumizu | 2010-11-02 |
| 7676770 | Apparatus and method for creating circuit diagram, program therefor and recording medium storing the program | — | 2010-03-09 |
| 6975026 | Package for mounting semiconductor device | Morihiko Mouri, Yasushi Takahashi, Takao Ono, Yosihiro Sakaguchi, Atsushi Nakamura +1 more | 2005-12-13 |
| 6496403 | Semiconductor memory device | Hiromasa Noda, Hiroshi Ichikawa, Hiroki Miyashita, Yasushi Takahashi | 2002-12-17 |