Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12101089 | Enhanced rising and falling transitions for level shifting low-voltage input signals | Xu Zhang | 2024-09-24 |
| 11705897 | Delay line with process-voltage-temperature robustness, linearity, and leakage current compensation | Xu Zhang, Shitong Zhao | 2023-07-18 |
| 11196410 | Method of generating precise and PVT-stable time delay or frequency using CMOS circuits | Zhengzheng Wu, Xu Zhang | 2021-12-07 |
| 10812056 | Method of generating precise and PVT-stable time delay or frequency using CMOS circuits | Zhengzheng Wu, Xu Zhang | 2020-10-20 |
| 10553531 | Process-invariant resistor and capacitor pair | Chao Song, Marzio Pedrali-Noy | 2020-02-04 |
| 10185337 | Low-power temperature-insensitive current bias circuit | Sungmin Ock, Wenjing Yin | 2019-01-22 |
| 10013010 | Voltage droop mitigation circuit for power supply network | Sungmin Ock | 2018-07-03 |
| 10003328 | Hybrid pulse-width control circuit with process and offset calibration | Wenjing Yin | 2018-06-19 |
| 9973081 | Low-power low-duty-cycle switched-capacitor voltage divider | Wenjing Yin, Sungmin Ock | 2018-05-15 |
| 9602433 | Systems and methods for sharing a serial communication port between a plurality of communication channels | Ankit Srivastava, Xiaohong Quan, Seyfollah Bazarjani | 2017-03-21 |
| 9478268 | Distributed clock synchronization | Philip Michael Clovis, Yi-Hung Tseng, Sushma Chilukuri | 2016-10-25 |
| 9437278 | Low latency synchronization scheme for mesochronous DDR system | Edwin Jose, Michael Drop, Raghu Sankuratri, Deepti Vijayalakshmi Sriramagiri, Marzio Pedrali-Noy | 2016-09-06 |
| 9191193 | Clock synchronization | Yi-Hung Tseng, Philip Michael Clovis, Sushma Chilukuri | 2015-11-17 |
| 9123408 | Low latency synchronization scheme for mesochronous DDR system | Edwin Jose, Michael Drop, Raghu Sankuratri, Deepti Vijayalakshmi Sriramagiri, Marzio Pedrali-Noy | 2015-09-01 |
| 8680891 | High voltage tolerant differential receiver | Ankit Srivastava, Xiaohong Quan | 2014-03-25 |
| 8446204 | High voltage tolerant receiver | Ankit Srivastava, Xiaohong Quan | 2013-05-21 |
| 8076963 | Delay-locked loop having a delay independent of input signal duty cycle variation | Xiaohong Quan | 2011-12-13 |