Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12301248 | Methods and systems of utilizing analog to digital converter (ADC) for multiply-accumulator (MAC) | Vishal Sarin, Biprangshu Saha, Sankha Saha, Sang Thanh Nguyen, Siraj Fulum Mossa | 2025-05-13 |
| 11961570 | Methods and systems of cell-array programming for neural compute using flash arrays | Vishal Sarin, Purval S. Sule, Siraj Fulum Mossa | 2024-04-16 |
| 11799489 | Temperature compensated common counter ADC method for neural compute | Vishal Sarin, Sankha Saha, Siraj Fulum | 2023-10-24 |
| 11687765 | Method for analog in-memory compute for neural networks | Vishal Sarin, Sankha Saha | 2023-06-27 |
| 7143257 | Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system | Fai Ching, Steven J. Schumann | 2006-11-28 |
| 7099226 | Functional register decoding system for multiple plane operation | Yolanda Yuan, Jason Guo, Sai K. Tsang, Steven J. Schumann | 2006-08-29 |
| 5973967 | Page buffer having negative voltage level shifter | Chinh Nguyen, Andy Yu, Vishal Sarin | 1999-10-26 |
| 5912842 | Nonvolatile PMOS two transistor memory cell and array | Shang-De Ted Chang, Andy Yu, Nader Radjy | 1999-06-15 |
| 5907484 | Charge pump | Andy Yu | 1999-05-25 |
| 5903497 | Integrated program verify page buffer | Andy Yu | 1999-05-11 |
| 5889440 | Adaptive frequency compensation technique | — | 1999-03-30 |
| 5798967 | Sensing scheme for non-volatile memories | Vishal Sarin, Andy Yu | 1998-08-25 |
| 5796656 | Row decoder circuit for PMOS non-volatile memory cell which uses electron tunneling for programming and erasing | Andy Yu, Jayson Trinh | 1998-08-18 |
| 5781471 | PMOS non-volatile latch for storage of redundancy addresses | Andy Yu | 1998-07-14 |
| 5777926 | Row decoder circuit for PMOS non-volatile memory cell which uses channel hot electrons for programming | Jayson Trinh, Andy Yu | 1998-07-07 |
| 5774406 | Switching circuit for controlled transition between high program and erase voltages and a power supply voltage for memory cells | — | 1998-06-30 |
| 5696728 | Negative voltage level shift circuit | Andy Yu | 1997-12-09 |
| 5687116 | Programming pulse ramp control circuit | Andy Yu | 1997-11-11 |
| 5625211 | Two-transistor electrically-alterable switch employing hot electron injection and fowler nordheim tunneling | — | 1997-04-29 |
| 5625544 | Charge pump | Andy Yu | 1997-04-29 |
| 5587603 | Two-transistor zero-power electrically-alterable non-volatile latch | — | 1996-12-24 |
| 5576568 | Single-transistor electrically-alterable switch employing fowler nordheim tunneling for program and erase | — | 1996-11-19 |
| 4975878 | Programmable memory data protection scheme | Sudhakar Boddu, Elroy M. Lucero | 1990-12-04 |
| 4873671 | Sequential read access of serial memories with a user defined starting address | Sudhakar Boddu, Elroy M. Lucero | 1989-10-10 |
| 4858185 | Zero power, electrically alterable, nonvolatile latch | Elroy M. Lucero | 1989-08-15 |