Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373365 | Bus interrupt debounce on a one-wire bidirectional bus | Lalan Jee Mishra, Ryan Scott Castro SPRING, Richard Dominic Wietfeldt, Jia Fu Cen | 2025-07-29 |
| 12283961 | Automatic clock rate synchronization for 1-wire radio frequency front-end interface | Lalan Jee Mishra, Richard Dominic Wietfeldt | 2025-04-22 |
| 12248365 | Error handling for a mixed mode RFFE bus | Lalan Jee Mishra, Richard Dominic Wietfeldt, Boris Alpin, Francesco Gatta | 2025-03-11 |
| 12124400 | Independent addressing of one-wire and two-wire devices on a shared RFFE bus interface | Lalan Jee Mishra, Francesco Gatta, Richard Dominic Wietfeldt | 2024-10-22 |
| 12124401 | Interrupt management on a one-wire bidirectional bus | Lalan Jee Mishra, Francesco Gatta, Richard Dominic Wietfeldt | 2024-10-22 |
| 12034469 | Variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus | Lalan Jee Mishra, Richard Dominic Wietfeldt, Karthik Manivannan | 2024-07-09 |
| 11907154 | Latency and power efficient clock and data recovery in a high-speed one-wire bidirectional bus | Lalan Jee Mishra, Francesco Gatta, Muhlis Kenan Ozel, Richard Dominic Wietfeldt | 2024-02-20 |
| 11886366 | One-wire bidirectional bus signaling with manchester encoding | Lalan Jee Mishra, Richard Dominic Wietfeldt | 2024-01-30 |
| 11513994 | Timed-trigger synchronization enhancement | Lalan Jee Mishra, Richard Dominic Wietfeldt | 2022-11-29 |
| 11327912 | Controlling the application time of radio frequency front end triggers based on execution of sequences | Reza RODD, Scott DAVENPORT, ZhenQi CHEN | 2022-05-10 |
| 11243902 | Intra-module serial communication interface for radio frequency devices | Reza RODD, Scott DAVENPORT, ZhenQi CHEN | 2022-02-08 |
| 11088815 | Techniques for timed-trigger and interrupt coexistence | Lalan Jee Mishra, Richard Dominic Wietfeldt, Karthik Manivannan | 2021-08-10 |
| 11041904 | Zero-pin test solution for integrated circuits | Tapan Jyoti Chakraborty, Rachana Rout | 2021-06-22 |
| 10614009 | Asynchronous interrupt with synchronous polling and inhibit options on an RFFE bus | Lalan Jee Mishra, Richard Dominic Wietfeldt, Helena Deirdre O'Shea, Wolfgang Roethig, Christopher Kong Yee Chun +4 more | 2020-04-07 |
| 8539188 | Method for enabling multi-processor synchronization | Mayan Moudgill, Vitaly Kalashnikov, Murugappan Senthilvelan, Tak-po Li, Pablo Balzola | 2013-09-17 |