SA

Sumit Arora

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
Overall (All Time): #2,024,510 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8977995 Timing budgeting of nested partitions for hierarchical integrated circuit designs Oleg Levitsky, Amit Kumar, Sushobhit Singh 2015-03-10
7865857 System and method for improved visualization and debugging of constraint circuit objects Amit Chopra, Ian Gebbie, Donald J. O'Riordan, Jean-Daniel Sonnard 2011-01-04