SJ

Steven K. Jenkins

IBM: 22 patents #4,909 of 70,183Top 7%
Overall (All Time): #196,773 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9436388 Memory access alignment in a double data rate (‘DDR’) system Robert Brian Likovich, Jr., Michael R. Trombley 2016-09-06
9343123 Memory access alignment in a double data rate (‘DDR’) system Robert Brian Likovich, Jr., Michael R. Trombley 2016-05-17
9053031 System and method for handling data access James J. Allen, Jr., James A. Mossman, Michael R. Trombley 2015-06-09
8902683 Memory access alignment in a double data rate (‘DDR’) system Robert Brian Likovich, Jr., Michael R. Trombley 2014-12-02
8547760 Memory access alignment in a double data rate (‘DDR’) system Robert Brian Likovich, Jr., Michael R. Trombley 2013-10-01
8140803 Structure for reducing latency associated with read operations in a memory system James J. Allen, Jr., James A. Mossman, Michael R. Trombley 2012-03-20
8032713 Structure for handling data access James J. Allen, Jr., James A. Mossman, Michael R. Trombley 2011-10-04
8028257 Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode James J. Allen, Jr., Michael R. Trombley 2011-09-27
7949830 System and method for handling data requests James J. Allen, Jr., James A. Mossman, Michael R. Trombley 2011-05-24
7937533 Structure for handling data requests James J. Allen, Jr., James A. Mossman, Michael R. Trombley 2011-05-03
7917908 Flow lookahead in an ordered semaphore management subsystem Ross Boyd Leavens, Robert Brian Likovich, Jr., Wesley Queen, Michael S. Siegel 2011-03-29
7660951 Atomic read/write support in a multi-module memory configuration Laura A. Weaver 2010-02-09
7660952 Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode James J. Allen, Jr., Michael R. Trombley 2010-02-09
7657771 Method and apparatus for reducing latency associated with read operations in a memory system James J. Allen, Jr., James A. Mossman, Michael R. Trombley 2010-02-02
7454753 Semaphore management subsystem for use with multi-thread processor systems Gordon Taylor Davis, Marco C. Heddes, Ross Boyd Leavens, Robert Brian Likovich, Jr. 2008-11-18
7406690 Flow lookahead in an ordered semaphore management subsystem Ross Boyd Leavens, Robert Brian Likovich, Jr., Wesley Queen, Michael S. Siegel 2008-07-29
7360035 Atomic read/write support in a multi-module memory configuration Laura A. Weaver 2008-04-15
7143414 Method and apparatus for locking multiple semaphores Marco C. Heddes, Ross Boyd Leavens, Robert Brian Likovich, Jr. 2006-11-28
7089555 Ordered semaphore management subsystem Jean Calvignac, Gordon Taylor Davis, Marco C. Heddes, Ross Boyd Leavens, Robert Brian Likovich, Jr. 2006-08-08
6977928 Method and system for data flow multicasting Brian Mitchell Bass, Jean Calvignac, Marco C. Heddes, Michael S. Siegel, Fabrice Jean Verplanken 2005-12-20
6633920 Method and system for network data flow management with improved completion unit Brian Mitchell Bass, Jean Calvignac, Marco C. Heddes, Michael S. Siegel, Fabrice Jean Verplanken 2003-10-14
6473838 Data transfer system for multiple network processors using dual DRAM storage Brian Mitchell Bass, Jean Calvignac, Marco C. Heddes, Michael S. Siegel, Michael R. Trombley +1 more 2002-10-29