Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6867732 | Embedded multi-functional preprocessing input data buffer in radar system | Shin-An Chen, Yu-Lin Su | 2005-03-15 |
| 6306711 | Method of fabricating a high-voltage lateral double diffused metal oxide semiconductor | — | 2001-10-23 |
| 6269315 | Reliability testing method of dielectric thin film | Kuan-Yu Fu, Chuan Liu, Donald Cheng, Mu-Chun Wang | 2001-07-31 |
| 6255809 | Method for measuring capacitance of passive device region | Yih-Jau Chang | 2001-07-03 |
| 6205013 | Multi-layer metallization capacitive structure for reduction of the simultaneous switching noise in integrated circuits | Jeng Gong, Jiann-Shiun Torng | 2001-03-20 |
| 6174760 | Method of improving vertical BJT gain | Yao-Chin Cheng | 2001-01-16 |
| 6165852 | Method of fabricating integration of high-voltage devices and low-voltage devices | Sheng-Lung Chen | 2000-12-26 |
| 6153913 | Electrostatic discharge protection circuit | Chen-Chung Hsu | 2000-11-28 |
| 6063674 | Method for forming high voltage device | Kuan-Yu Fu | 2000-05-16 |
| 6040601 | High voltage device | Jeng Gong | 2000-03-21 |
| 5966608 | Method of forming high voltage device | Jeng Gong | 1999-10-12 |
| 5894155 | Metal gate high voltage integrated circuit/process | — | 1999-04-13 |
| 5686347 | Self isolation manufacturing method | — | 1997-11-11 |
| 5624857 | Process for fabricating double well regions in semiconductor devices | — | 1997-04-29 |
| 5614421 | Method of fabricating junction termination extension structure for high-voltage diode devices | — | 1997-03-25 |
| 5589411 | Process for fabricating a high-voltage MOSFET | Shing-Ren Sheu | 1996-12-31 |
| 5576569 | Electrically programmable and erasable memory device with depression in lightly-doped source | Jyn-Kuang Lin | 1996-11-19 |
| 5574306 | Lateral bipolar transistor and FET | Ying-Tzung Wang | 1996-11-12 |
| 5569613 | Method of making bipolar junction transistor | — | 1996-10-29 |
| 5554543 | Process for fabricating bipolar junction transistor having reduced parasitic capacitance | — | 1996-09-10 |
| 5550064 | Method for fabricating high-voltage complementary metal-oxide-semiconductor transistors | — | 1996-08-27 |
| 5547895 | Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions | — | 1996-08-20 |
| 5523246 | Method of fabricating a high-voltage metal-gate CMOS device | — | 1996-06-04 |
| 5518938 | Process for fabricating a CMOS transistor having high-voltage metal-gate | — | 1996-05-21 |
| 5514890 | Electrically erasable programmable memory device with improved erase and write operation | Jyh-Kung Lin | 1996-05-07 |