Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7941636 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Le Trong Nguyen | 2011-05-10 |
| 7685402 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Le Trong Nguyen | 2010-03-23 |
| 7555631 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Le Trong Nguyen | 2009-06-30 |
| 7409097 | Video encoding using variable bit rates | Dengzhi Zhang, Stanley H. Siu | 2008-08-05 |
| 6934332 | Motion estimation using predetermined pixel patterns and subpatterns | Cheung Auyeung, Stanley H. Siu | 2005-08-23 |
| 6891890 | Multi-phase motion estimation system and method | Cheung Auyeung, Stanley H. Siu | 2005-05-10 |
| 6813315 | Motion estimation using multiple search windows | Cheung Auyeung, Stanley H. Siu | 2004-11-02 |
| 6249856 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiy Garg, Derek J. Lentz, Le Trong Nguyen | 2001-06-19 |
| 6044449 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiy Garg, Derek J. Lentz, Le Trong Nguyen | 2000-03-28 |
| 5838986 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Le Trong Nguyen | 1998-11-17 |
| 5731850 | Hybrid hierarchial/full-search MPEG encoder motion estimation | Gregory V. Maturi, Vivek Bhargava, Ren Wang | 1998-03-24 |
| 5682546 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Le Trong Nguyen | 1997-10-28 |
| 5610659 | MPEG encoder that concurrently determines video data encoding format and rate control | Gregory C. Maturi, Vivek Bhargava, Ren Wang, Richard H. Tom | 1997-03-11 |
| 5560035 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Le Trong Nguyen | 1996-09-24 |
| 5493687 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Le Trong Nguyen | 1996-02-20 |
| 4837748 | Counting RAM | Shine C. Chung, Siu K. Tsang, James T. Koo, John Y. Chan | 1989-06-06 |