Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9589879 | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates | Valentin Kosenko | 2017-03-07 |
| 9515024 | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor | Valentin Kosenko | 2016-12-06 |
| 9323010 | Structures formed using monocrystalline silicon and/or other materials for optical and other applications | Valentin Kosenko, Edward Lee McBain, Cyprian Emeka Uzoh, Pezhman Monadgemi | 2016-04-26 |
| 9142511 | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers | Valentin Kosenko | 2015-09-22 |
| 9111902 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Valentin Kosenko, James J. Roman | 2015-08-18 |
| 9018094 | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates | Valentin Kosenko | 2015-04-28 |
| 8829683 | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers | Valentin Kosenko | 2014-09-09 |
| 8757897 | Optical interposer | Valentin Kosenko, Edward Lee McBain, Cyprian Emeka Uzoh, Pezhman Monadgemi | 2014-06-24 |
| 8633589 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Valentin Kosenko, James J. Roman | 2014-01-21 |
| 8431431 | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers | Valentin Kosenko | 2013-04-30 |
| 7964508 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Valentin Kosenko, James J. Roman | 2011-06-21 |
| 7521360 | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby | Patrick Halahan, Sam Kao, Bosco Lan, Oleg Siniaguine | 2009-04-21 |
| 7510928 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Valentin Kosenko, James J. Roman | 2009-03-31 |
| 7241641 | Attachment of integrated circuit structures and other substrates to substrates with vias | Sam Kao | 2007-07-10 |
| 7241675 | Attachment of integrated circuit structures and other substrates to substrates with vias | Sam Kao | 2007-07-10 |
| 7186586 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities | Patrick B. Halahan, Sam Kao | 2007-03-06 |
| 7060601 | Packaging substrates for integrated circuits and soldering methods | Patrick B. Halahan, Sam Kao | 2006-06-13 |
| 7049170 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities | Patrick B. Halahan, Sam Kao | 2006-05-23 |
| 7034401 | Packaging substrates for integrated circuits and soldering methods | Patrick B. Halahan, Sam Kao | 2006-04-25 |
| 6897148 | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby | Patrick Halahan, Sam Kao, Bosco Lan, Oleg Siniaguine | 2005-05-24 |
| 6749764 | Plasma processing comprising three rotational motions of an article being processed | Oleg Siniaguine, Patrick Halahan, Sam Kao | 2004-06-15 |
| 6693361 | Packaging of integrated circuits and vertical integration | Oleg Siniaguine | 2004-02-17 |
| 6667242 | Brim and gas escape for non-contact wafer holder | Oleg Siniaguine, Alex Berger | 2003-12-23 |
| 6498074 | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners | Oleg Siniaguine, Patrick B. Halahan | 2002-12-24 |
| 6448153 | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners | Oleg Siniaguine, Patrick B. Halahan | 2002-09-10 |