Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11620500 | Synapse system and synapse method to realize STDP operation | Frederick Chen, Ping Wang, Shao-Ching Liao, Chih-Cheng Fu, Ming-Che Lin +1 more | 2023-04-04 |
| 11520526 | Write method for resistive memory | Ping Wang, Shao-Ching Liao, Chien-Min Wu, Chia-Hua Ho, Frederick Chen +1 more | 2022-12-06 |
| 11398256 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays | Chang Hua Siau, Christophe J. Chevallier, Darrell Rinerson, Sri Rama Namala | 2022-07-26 |
| 11314588 | Memory device and multi physical cells error correction method thereof | Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Ngatik Cheung | 2022-04-26 |
| 11270764 | Two-bit memory cell and circuit structure calculated in memory thereof | WEI-DONG CONG | 2022-03-08 |
| 11088711 | Memory apparatus and data accessing method thereof | Chuen-Der Lien, Chi-Shun Lin, Ngatik Cheung | 2021-08-10 |
| 11069386 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Christophe J. Chevallier, Chang Hua Siau | 2021-07-20 |
| 11055021 | Resistive memory | Ping Wang, Shao-Ching Liao, Chien-Min Wu, Chia-Hua Ho, Frederick Chen +1 more | 2021-07-06 |
| 11010245 | Memory storage apparatus with dynamic data repair mechanism and method of dynamic data repair thereof | Chuen-Der Lien, Ming-Huei Shieh, Ngatik Cheung, Chi-Shun Lin | 2021-05-18 |
| 10937495 | Resistive memory apparatus and method for writing data thereof | He-Hsuan Chao, Ping Wang, Norio Hattori, Chien-Min Wu, Chih-Hua HUNG | 2021-03-02 |
| 10853167 | Memory apparatus having hierarchical error correction code layer | Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Ngatik Cheung | 2020-12-01 |
| 10811092 | RRAM with plurality of 1TnR structures | Chi-Shun Lin, Chuen-Der Lien, Douk-Hyoun Ryu, Ming-Huei Shieh | 2020-10-20 |
| 10714157 | Non-volatile memory and reset method thereof | Ming-Che Lin, He-Hsuan Chao, Ping Wang, Ngatik Cheung, Chia-Wen Cheng | 2020-07-14 |
| 10700878 | Physical unclonable function code generation apparatus and method thereof | Douk-Hyoun Ryu | 2020-06-30 |
| 10650870 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Christophe J. Chevallier, Chang Hua Siau | 2020-05-12 |
| 10622028 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays | Chang Hua Siau, Christophe J. Chevallier, Darrell Rinerson, Sri Rama Namala | 2020-04-14 |
| 10514980 | Encoding method and memory storage apparatus using the same | Chuen-Der Lien, Ming-Huei Shieh, Ngatik Cheung, Chi-Shun Lin | 2019-12-24 |
| 10490272 | Operating method of resistive memory element | Lih-Wei Lin, Tsung-Huan Tsai, Chi-Shun Lin | 2019-11-26 |
| 10439829 | Physical unclonable function code generating method and providing apparatus thereof | Lih-Wei Lin, Chi-Shun Lin | 2019-10-08 |
| 10419004 | NVFF monotonic counter and method of implementing same | Chi-Shun Lin | 2019-09-17 |
| 10372535 | Encoding method and a memory storage apparatus using the same | Chuen-Der Lien, Ming-Huei Shieh, Ngatik Cheung, Chi-Shun Lin | 2019-08-06 |
| 10261692 | Non-volatile memory and erase controlling method thereof | — | 2019-04-16 |
| 10262732 | Programmable array logic circuit and operating method thereof | Chi-Shun Lin, Douk-Hyoun Ryu, Ngatik Cheung | 2019-04-16 |
| 10216570 | Memory device and control method thereof | Hsi-Hsien Hung | 2019-02-26 |
| 10210917 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Christophe J. Chevallier, Chang Hua Siau | 2019-02-19 |