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Wide frequency range DLL with dynamically determined VCDL/VCO operational states |
— |
2007-06-19 |
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System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output |
Suwei Chen |
2006-11-14 |
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Data path configurable for multiple clocking arrangements |
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Multi-port memory cell and access method |
Jeffery Scott Hunt, George M. Ansel |
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Delay circuit that scales with clock cycle time |
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Method and circuitry for writing data |
George M. Ansel, William G. Baker, James E. Kelly |
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Self-timed synchronous pulse generator with test mode |
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2000-08-08 |
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Write enabling circuitry for a semiconductor memory |
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