Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520877 | Apparatus and method for detecting or repairing minimum delay errors | Pascal A. Meinerzhagen, James W. Tschanz, Vivek K. De | 2016-12-13 |
| 7197721 | Weight compression/decompression system | Srinivas Patil | 2007-03-27 |
| 7096397 | Dft technique for avoiding contention/conflict in logic built-in self-test | Sanjay Sengupta, Rajesh Galivanche | 2006-08-22 |
| 7036063 | Generalized fault model for defects and circuit marginalities | Sanjay Sengupta, Dhiraj Goswami | 2006-04-25 |
| 6973422 | Method and apparatus for modeling and circuits with asynchronous behavior | Sitaram Yadavalli | 2005-12-06 |
| 6938225 | Scan design for double-edge-triggered flip-flops | — | 2005-08-30 |
| 6912701 | Method and apparatus for power supply noise modeling and test pattern development | — | 2005-06-28 |
| 6715091 | System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation | — | 2004-03-30 |
| 6510398 | Constrained signature-based test | Sanjay Sengupta, Rajesh Galivanche | 2003-01-21 |
| 5796751 | Technique for sorting high frequency integrated circuits | — | 1998-08-18 |
| 5793777 | System and method for testing internal nodes of an integrated circuit at any predetermined machine cycle | — | 1998-08-11 |
| 5629858 | CMOS transistor network to gate level model extractor for simulation, verification and test generation | Andreas Kuehlmann, Arvind Srinivasan | 1997-05-13 |
| 5297151 | Adjustable weighted random test pattern generator for logic circuits | Matthias Gruetzner, Leendert M. Huisman, Cordt Starke | 1994-03-22 |