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FinFET device having a partially dielectric isolated fin structure |
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Device and method for alignment of vertically stacked wafers and die |
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Method for the formation of a FinFET device with epitaxially grown source-drain regions having a reduced leakage path |
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Method for the formation of a FinFET device having partially dielectric isolated fin structure |
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Method for the formation of a FinFET device having partially dielectric isolated Fin structure |
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John H. Zhang, Walter Kleemeier, Paul Ferreira |
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Copper interconnect structure having a graphene cap |
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Use of acoustic spectral analysis for monitoring/control of CMP processes |
— |
2002-07-23 |
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Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby |
Todd H. Gandy, Robert Louis Hodges |
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Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby |
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Method and apparatus for real-time wafer temperature and thin film growth measurement and control in a lamp-heated rapid thermal processor |
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1994-05-17 |