Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7598146 | Self-aligned gate and method | — | 2009-10-06 |
| 7126190 | Self-aligned gate and method | — | 2006-10-24 |
| 6774001 | Self-aligned gate and method | — | 2004-08-10 |
| 6661064 | Memory masking for periphery salicidation of active regions | Loi N. Nguyen | 2003-12-09 |
| 6514811 | Method for memory masking for periphery salicidation of active regions | Loi N. Nguyen | 2003-02-04 |
| 6284584 | Method of masking for periphery salicidation of active regions | Loi N. Nguyen | 2001-09-04 |
| 6107194 | Method of fabricating an integrated circuit | Loi N. Nguyen | 2000-08-22 |
| 6087709 | Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby | Todd H. Gandy, Ronald K. Sampson | 2000-07-11 |
| 6051864 | Memory masking for periphery salicidation of active regions | Loi N. Nguyen | 2000-04-18 |
| 6040233 | Method of making a shallow trench isolation with thin nitride as gate dielectric | — | 2000-03-21 |
| 6022788 | Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby | Todd H. Gandy, Ronald K. Sampson | 2000-02-08 |
| 6011711 | SRAM cell with p-channel pull-up sources connected to bit lines | Frank J. Sigmund | 2000-01-04 |
| 5977607 | Method of forming isolated regions of oxide | Frank R. Bryant, Fusen Chen, Che-Chia Wei | 1999-11-02 |
| 5952707 | Shallow trench isolation with thin nitride as gate dielectric | — | 1999-09-14 |
| 5927992 | Method of forming a dielectric in an integrated circuit | Frank R. Bryant | 1999-07-27 |
| 5831897 | SRAM memory cell design having complementary dual pass gates | — | 1998-11-03 |
| 5811865 | Dielectric in an integrated circuit | Frank R. Bryant | 1998-09-22 |
| 5793114 | Self-aligned method for forming contact with zero offset to gate | Loi N. Nguyen | 1998-08-11 |
| 5742095 | Method of fabricating planar regions in an integrated circuit | Frank R. Bryant | 1998-04-21 |
| 5729036 | Integrated circuit transistor having drain junction offset | Frank R. Bryant | 1998-03-17 |
| 5682052 | Method for forming isolated intra-polycrystalline silicon structure | Frank R. Bryant | 1997-10-28 |
| 5543343 | Method fabricating an integrated circuit | Frank R. Bryant | 1996-08-06 |
| 5541455 | Method of forming low resistance contacts at the junction between regions having different conductivity types | — | 1996-07-30 |
| 5506440 | Poly-buffered LOCOS process | Che-Chia Wei, Frank R. Bryant | 1996-04-09 |
| 5460983 | Method for forming isolated intra-polycrystalline silicon structures | Frank R. Bryant | 1995-10-24 |